U631H256
Not Recommended For New Designs
SoftStore
32K x 8 nvSRAM
Features
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
25 ns Access Times
10 ns Output Enable Access
Times
Software STORE Initiation
Automatic STORE Timing
10
6
STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Unlimited Read and Write to
SRAM
Single 5 V
±
10 % Operation
Operating temperature ranges:
0 to 70
°C
-40 to 85
°C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Package: SOP28 (330 mil)
Description
The U631H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H256 is a fast static RAM
(25 ns), with a nonvolatile electri-
cally erasable PROM (EEPROM)
element incorporated in each static
memory cell. The SRAM can be
read and written an unlimited num-
ber of times, while independent
nonvolatile
data
resides
in
EEPROM. Data transfers from the
SRAM to the EEPROM (the
STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
The U631H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U631H256 is pin compatible
with standard SRAMs.
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
SOP
21
20
19
18
17
16
15
Top View
August 15, 2006
STK Control #ML0043
1
Rev 1.1
U631H256
Block Diagram
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E
W
Input Buffers
EEPROM Array
512 x (64 x 8)
STORE
Row Decoder
SRAM
Array
512 Rows x
64 x 8 Columns
Store/
Recall
Control
V
CC
V
SS
RECALL
V
CC
Column I/O
Column Decoder
Software
Detect
A0 - A13
A0 A1 A2 A3 A4 A10
G
Truth Table for SRAM Operations
Operating Mode
Standby/not selected
Internal Read
Read
Write
*
H or L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
E
H
L
L
L
W
*
G
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
H
H
L
H
L
*
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
C-Type
K-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
T
stg
Min.
-0.5
-0.3
-0.3
Max.
7
V
CC
+0.5
V
CC
+0.5
1
Unit
V
V
V
W
°C
°C
°C
0
-40
-65
70
85
150
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK Control #ML0043
2
Rev 1.1
August 15, 2006
U631H256
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage
Input High Voltage
Symbol
V
CC
V
IL
V
IH
-2 V at Pulse Width
10 ns permitted
Conditions
Min.
4.5
-0.3
2.2
Max.
5.5
0.8
V
CC
+0.3
Unit
V
V
V
C-Type
DC Characteristics
Operating Supply Current
b
Symbol
I
CC1
V
CC
V
IL
V
IH
t
c
Conditions
Min.
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
95
Max.
K-Type
Unit
Min.
Max.
100
mA
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
V
CC
W
V
IL
V
IH
V
CC
E
t
c
= 5.5 V
≥
V
CC
-0.2 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 5.5 V
≥
V
IH
= 25 ns
6
7
mA
Average Supply Current
at t
cR
= 200 ns
b
(Cycling CMOS Input Levels)
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC3
20
20
mA
I
CC(SB)1
40
42
mA
Standby Supply Curent
d
(Stable CMOS Input Levels)
I
CC(SB)
V
CC
E
V
IL
V
IH
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
1
2
mA
b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
c: I
CC2
is the average current required for the duration of the STORE cycle (t
STORE
).
d: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
August 15, 2006
STK Control #ML0043
3
Rev 1.1
U631H256
DC Characteristics
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
High
Low
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
I
IH
I
IL
Symbol
V
CC
I
OH
I
OL
V
CC
V
OH
V
OL
V
CC
V
IH
V
IL
V
CC
E or G
V
OH
V
OL
Conditions
= 4.5 V
=-4 mA
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0V
= 5.5 V
≥
V
IH
= 5.5 V
= 0V
1
-1
μA
μA
Min.
Max.
Unit
V
OH
V
OL
I
OH
I
OL
2.4
0.4
-4
8
V
V
mA
mA
1
-1
μA
μA
SRAM Memory Operation
Switching Characteristics
No.
Read Cycle
1
2
3
4
5
6
7
8
9
Read Cycle Time
f
Address Access Time to Data Valid
g
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data
Valid
E HIGH to Output in High-Z
h
G HIGH to Output in High-Z
h
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time after Addr. Change
g
Symbol
Unit
Alt.
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
ELQX
t
GLQX
t
AXQX
t
ELICCH
t
EHICCL
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
5
0
3
0
25
Min. Max.
25
25
25
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 Chip Enable to Power Active
e
11 Chip Disable to Power Standby
d, e
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both Low.
Address valid prior to or coincident with E transition LOW.
Measured
±
200 mV from steady state output voltage.
STK Control #ML0043
4
Rev 1.1
August 15, 2006
U631H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
t
cR
(1)
Ai
Previous Data Valid
t
v(A)
(9)
Address Valid
t
a(A)
(2)
Output Data Valid
DQi
Output
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
t
cR
(1)
Ai
E
G
DQi
Output
High Impedance
Address Valid
t
a(A)
t
a(E)
(2)
(3)
t
en(E)
(7)
t
a(G)
t
en(G)
(8)
t
PU
(10)
ACTIVE
STANDBY
(4)
t
dis(E)
(5)
t
PD
(11)
t
dis(G)
(6)
Output Data Valid
I
CC
No. Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of
Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z
Symbol
Unit
Alt. #1
Alt. #2
IEC
Min.
Max.
t
AVAV
t
WLWH
t
AVAV
t
cW
t
w(W)
25
20
20
0
20
20
20
10
0
0
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WLEH
t
AVWL
t
AVWH
t
ELWH
t
ELEH
t
DVWH
t
WHDX
t
WHAX
t
WLQZ
t
WHQX
t
DVEH
t
EHDX
t
EHAX
t
AVEL
t
AVEH
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
August 15, 2006
STK Control #ML0043
5
Rev 1.1
Analogue and Mixed Signal
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