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L64212GM-30

Description
Video Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size323KB,12 Pages
ManufacturerLSC/CSI
Websitehttps://lsicsi.com
Download Datasheet Parametric Compare View All

L64212GM-30 Overview

Video Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95

L64212GM-30 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codePGA
package instructionPGA,
Contacts95
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Other features2 X 9 BIT INPUT BUS; 4 X 9 BIT OUTPUT BUS
boundary scanNO
maximum clock frequency30 MHz
External data bus width9
JESD-30 codeS-CPGA-P95
JESD-609 codee0
length37.085 mm
low power modeYES
Number of terminals95
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output data bus width9
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height4.47 mm
Maximum supply voltage6 V
Minimum supply voltage3 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width37.085 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, VIDEO SHIFT REGISTER
Base Number Matches1

L64212GM-30 Related Products

L64212GM-30 L64212GC-30
Description Video Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95 Video Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95
Is it Rohs certified? incompatible incompatible
Parts packaging code PGA PGA
package instruction PGA, CERAMIC, PGA-95
Contacts 95 95
Reach Compliance Code unknown unknown
ECCN code 3A001.A.2.C 3A991.A.2
Other features 2 X 9 BIT INPUT BUS; 4 X 9 BIT OUTPUT BUS 2 X 9 BIT INPUT BUS; 4 X 9 BIT OUTPUT BUS
boundary scan NO NO
maximum clock frequency 30 MHz 30 MHz
External data bus width 9 9
JESD-30 code S-CPGA-P95 S-CPGA-P95
JESD-609 code e0 e0
length 37.085 mm 37.085 mm
low power mode YES YES
Number of terminals 95 95
Maximum operating temperature 125 °C 70 °C
Output data bus width 9 9
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code PGA PGA
Package shape SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Certification status Not Qualified Not Qualified
Maximum seat height 4.47 mm 4.47 mm
Maximum supply voltage 6 V 6 V
Minimum supply voltage 3 V 3 V
Nominal supply voltage 5 V 5 V
surface mount NO NO
technology CMOS CMOS
Temperature level MILITARY COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form PIN/PEG PIN/PEG
Terminal pitch 2.54 mm 2.54 mm
Terminal location PERPENDICULAR PERPENDICULAR
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 37.085 mm 37.085 mm
uPs/uCs/peripheral integrated circuit type DSP PERIPHERAL, VIDEO SHIFT REGISTER DSP PERIPHERAL, VIDEO SHIFT REGISTER
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