L64212GC-30 datasheet, PDF - EEWORLD Datasheet

L64212GC-30: DescriptionVideo Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95; CategoryThe embedded processor and controller Microcontrollers and processors; File Size323KB，12 Pages; ManufacturerLSC/CSI; Websitehttps://lsicsi.com

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L64212GC-30 Overview

Video Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	LSC/CSI
Parts packaging code	PGA
package instruction	CERAMIC, PGA-95
Contacts	95
Reach Compliance Code	unknown
ECCN code	3A991.A.2
Other features	2 X 9 BIT INPUT BUS; 4 X 9 BIT OUTPUT BUS
boundary scan	NO
maximum clock frequency	30 MHz
External data bus width	9
JESD-30 code	S-CPGA-P95
JESD-609 code	e0
length	37.085 mm
low power mode	YES
Number of terminals	95
Maximum operating temperature	70 °C
Minimum operating temperature
Output data bus width	9
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	4.47 mm
Maximum supply voltage	6 V
Minimum supply voltage	3 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	37.085 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, VIDEO SHIFT REGISTER

	L64212GC-30	L64212GM-30
Description	Video Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95	Video Shift Register, 9-Bit, CMOS, CPGA95, CERAMIC, PGA-95
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	PGA	PGA
package instruction	CERAMIC, PGA-95	PGA,
Contacts	95	95
Reach Compliance Code	unknown	unknown
ECCN code	3A991.A.2	3A001.A.2.C
Other features	2 X 9 BIT INPUT BUS; 4 X 9 BIT OUTPUT BUS	2 X 9 BIT INPUT BUS; 4 X 9 BIT OUTPUT BUS
boundary scan	NO	NO
maximum clock frequency	30 MHz	30 MHz
External data bus width	9	9
JESD-30 code	S-CPGA-P95	S-CPGA-P95
JESD-609 code	e0	e0
length	37.085 mm	37.085 mm
low power mode	YES	YES
Number of terminals	95	95
Maximum operating temperature	70 °C	125 °C
Output data bus width	9	9
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.47 mm	4.47 mm
Maximum supply voltage	6 V	6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	37.085 mm	37.085 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, VIDEO SHIFT REGISTER	DSP PERIPHERAL, VIDEO SHIFT REGISTER

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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