Z380 Microprocessor
Product Specification
Warning:
DO NOT USE IN LIFE SUPPORT
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ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
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INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
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trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
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Z380 Microprocessor
Product Specification
FEATURES
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Static CMOS Design with Low-Power Standby Mode Option
32-Bit Internal Data Paths and ALU
Operating Frequency
–
DC-to-18 MHz at 5V
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DC-to-10 MHz at 3.3V
Enhanced Instruction Set that Maintains Object-Code Compatibility with Z80
®
and
Z180 Microprocessors
16-Bit (64K) or 32-Bit (4G) Linear Address Space
16-Bit Data Bus with Dynamic Sizing
Two-Clock Cycle Instruction Execution Minimum
Four Banks of On-Chip Register Files
Enhanced Interrupt Capabilities, Including 16-Bit Vector
Undefined Opcode Trap for Z380™ Instruction Set
On-Chip I/O Functions:
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Six-Memory Chip Selects with Programmable Waits
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Programmable I/O Waits
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DRAM Refresh Controller
100-Pin QFP Package
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Z380 Microprocessor
Product Specification
GENERAL DESCRIPTION
The Z380 Microprocessor is an integrated high-performance microprocessor with fast and
efficient throughput and increased memory addressing capabilities. The Z380 offers a con-
tinuing growth path for present Z80-or Z180-based designs, while maintaining Z80
®
CPU
and Z180 MPU object-code compatibility. The Z380 MPU enhancements include an
improved 280 CPU, expanded 4-Gbyte space and flexible bus interface timing.
An enhanced version of the Z80 CPU is key to the Z380 MPU. The basic addressing
modes of the Z80 microprocessor have been augmented as follows: Stack Pointer Relative
loads and stores, 16-bit and 24-bit indexed offsets, and more flexible Indirect Register
addressing, with all of the addressing modes allowing access to the entire 32-bit address
space. Additions made to the instruction set, include a full complement of 16-bit arithme-
tic and logical operations, 16-bit I/O operations, multiply and divide, plus a complete set
of register-to-register loads and exchanges.
The expanded basic register file of the Z80 MPU microprocessor includes alternate regis-
ter versions of the IX and IY registers. There are four sets of this basic Z80 microproces-
sor register file present in the Z380 MPU, along with the necessary resources to manage
switching between the different register sets. All of the register-pairs and index registers in
the basic Z80 microprocessor register file are expanded to 32 bits.
The Z380 MPU expands the basic 64 Kbyte Z80 and Z180 address space to a full 4 Gbyte
(32-bit) address space. This address space is linear and completely accessible to the user
program. The I/O address space is similarly expanded to a full 4 Gbyte (32-bit) range and
16-bit I/O, and both simple and block move are added.
Some features that have traditionally been handled by external peripheral devices have
been incorporated in the design of the Z380 microprocessor. The on-chip peripherals
reduce system chip count and reduce interconnection on the external bus. The Z380 MPU
contains a refresh controller for DRAMs that employs a /CAS-before-/RAS refresh cycle
at a programmable rate and burst size.
Six programmable memory-chip selects are available, along with programmable wait-
state generators for each chip-select address range.
The Z380 MPU provides flexible bus interface timing, with separate control signals and
timing for memory and I/O. The memory bus control signals provide timing references
suitable for direct interface to DRAM, static RAM, EPROM, or ROM. Full control of the
memory bus timing is possible because the /WAIT signal is sampled three times during a
memory transaction, allowing complete user control of edge-to-edge timing between the
reference signals provided by the Z380 MPU. The I/O bus control signals allow direct
interface to members of the Z80 family of peripherals, the Z8000 family of peripherals, or
the Z8500 series of peripherals. Figure 1 shows the Z380 block diagram; Figure 2 shows
the pin assignments.
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