DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16724
480-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256-GRAY SCALE)
DESCRIPTION
The
µ
PD16724 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scale. Data input is
based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216
colors by output of 256 values
γ
-corrected by an internal D/A converter and 9-by-2 external power modules.
Because the output dynamic range is as large as V
SS2
+ 0.2 V to V
DD2
−
0.2 V, level inversion operation of the LCD’s
common electrode is rendered unnecessary. It corresponds to the 2 x 2-dot inversion drive at the time of single-
sided mounting. The maximum clock frequency is 55 MHz when driving at 3.0 V.
FEATURES
•
CMOS level input
•
480 outputs
•
Input of 8 bits (gray scale data) by 6 dots
•
Capable of outputting 256 values by means of 9-by-2 external power modules (18 units) and a D/A converter
5
•
Logic power supply voltage (V
DD1
): 2.3 to 3.6 V
•
Driver power supply voltage (V
DD2
): 12.0 to 15.0 V (switchable: LPC)
•
Output dynamic range: V
SS2
+ 0.2 V to V
DD2
−
0.2 V
•
High-speed data transfer: f
CLK
= 55 MHz MAX. (internal data transfer speed when operating at V
DD1
= 3.0 V)
•
Apply for 2 x 2 dot-line inversion
•
Output voltage polarity inversion function (POL)
•
Input data inversion function (POL21, POL22)
•
Output reset control (MODE1)
•
Slew rate control mode switching (MODE2)
•
Slew rate control (SRC1, SRC2)
•
Bias current control (LPC)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16724N-xxx
Remark
The TCP’s external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16086EJ1V0DS00 (1st edition)
Date Published March 2003 NS CP (K)
Printed in Japan
The mark
5
shows major revised points.
2002
µ
PD16724
5
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
C
1
C
2
80-bit bidirectional shift register
C
79
C
80
STHL
V
DD1
V
SS1
D
00
-D
07
D
10
-D
17
D
20
-D
27
D
30
-D
37
D
40
-D
47
D
50
-D
57
POL21, POL22
MODE1, MODE2
SRC1, SRC2
LPC
Data register
POL
Latch
V
DD2
Level shifter
V
SS2
D/A converter
V
0
-V
17
Voltage follower output
S
1
S
2
S
3
S
480
Remark
/xxx indicates active low signal.
2
Data Sheet S16086EJ1V0DS
µ
PD16724
2. PIN CONFIGURATION (
µ
PD16724N-xxx) (Copper Foil Surface, Face-up)
STHL
D
57
D
56
:
D
51
D
50
D
47
D
46
:
D
41
D
40
D
37
D
36
:
D
31
D
30
SRC2
MODE2
V
DD1
R,/L
V
17
V
16
V
15
V
14
V
13
V
12
V
11
V
10
V
9
V
DD2
V
SS2
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
MODE1
V
SS1
LPC
CLK
SRC1
STB
POL
POL22
POL21
D
27
D
26
:
D
21
D
20
D
17
D
16
:
D
11
D
10
D
07
D
06
:
D
01
D
00
STHR
S
480
S
479
S
478
Copper Foil
Surface
S
3
S
2
S
1
Remark
This figure does not specify the TCP package.
Data Sheet S16086EJ1V0DS
3
µ
PD16724
3. PIN FUNCTIONS
(1/3)
Pin Symbol
S
1
to S
480
D
00
to D
07
D
10
to D
17
D
20
to D
27
D
30
to D
37
D
40
to D
47
D
50
to D
57
R,/L
Shift direction control
Input
The shift direction control pin of shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift) : STHR (input)
→S
1
→S
480
→STHL
(output)
R,/L = L (left shift) : STHL (input)
→S
480
→S
1
→STHR
(output)
STHR
Right shift start pulse
I/O
These are the start pulse input/output pins when connected in cascade.
Loading of display data starts when a high level is read at the rising edge of
CLK.
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2 CLK, the first 1 CLK of the high-level
input is valid.
STHL
Left shift start pulse
I/O
At the rising edge of the 80th clock after the start pulse input, the start pulse
output reaches the high level, thus becoming the start pulse of the next-level
driver. The high-level width outputted is 1 CLK.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
CLK
Shift clock
Input
The shift clock input pin of shift register. The display data is loaded into the
data register at the rising edge.
If 82 clock pulses are input after input of the start pulse, input of display data
is halted automatically. The contents of the shift register are cleared at the
STB’s rising edge.
STB
Latch
Input
The contents of the data register are transferred to the latch circuit at the
rising edge. In addition, at the falling edge, the gray scale voltage is supplied
to the driver. It is necessary to ensure input of one pulse per horizontal
period.
SRC1
Slew rate control 1
Input
SRC1 is good at the time of MODE2 = H. SRC1 is pulled up to the V
DD1
in the
IC.
SRC1 = H: High slew rate mode (large current consumption)
SRC1 = L: Low slew rate mode (small current consumption)
Refer to
6. RELATIONSHIP BETWEEN MODE2, SRC1 AND SRC2
for
details.
SRC2
Slew rate control 2
Input
SRC2 is good at the time of MODE2 = L or open. SRC2 is pulled down to the
V
SS1
in the IC.
SRC2 = H: High slew rate period is twice the STB width from STB rising.
SRC2 = L or open: High slew rate period is 3 times the STB width from STB
rising.
Refer to
6. RELATIONSHIP BETWEEN MODE2, SRC1 AND SRC2
for
details.
Port 2 display data
Input
Driver
Port 1 display data
Pin Name
I/O
Output
Input
Description
The D/A converted 256-gray-scale analog voltage is output.
The display data is input with a width of 48 bits, viz., the gray scale data
(8 bits) by 6 dots (2 pixels).
D
X0
: LSB, D
X7
: MSB
4
Data Sheet S16086EJ1V0DS
µ
PD16724
(2/3)
Pin Symbol
POL
Pin Name
Polarity input
I/O
Input
Description
The relation between POL and output is as follows.
POL
S
12n
, S
12n
−3
, S
12n
−4
, S
12n
−7
,
S
12n
−8
, S
12n
−11
Note
L
H
V
0
to V
8
V
9
to V
17
S
12n
−1
, S
12n
−2
, S
12n
−5
, S
12n
−6
,
S
12n
−9
, S
12n
−10
Note
V
9
to V
17
V
0
to V
8
Note
n = 1,2, ..., 80
Input of the POL signal is allowed the setup time (t
POL-STB
) with respect to STB’s
rising edge.
MODE1 = H or open:
When it switches such as POL = H→L or L→H, all output pins are output reset
during STB = H. When it does not switch, all output pins become Hi-Z during
STB = H. Refer to
7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC,
POL AND OUTPUT WAVEFORM
for details.
MODE1
Output reset control
Input
MODE1 is pulled up to the V
DD1
in the IC.
MODE1 = H or open: During an STB = H period, output is reset between all-
output pins.
MODE1 = L: During an STB = H period, output is Hi-Z between all-output pins.
MODE2
Slew rate control
mode switching
Input
MODE2 is pulled down to the V
SS1
in the IC.
MODE2 = H: High slew rate period is controlled from the outside (SRC1 is
good).
MODE2 = L or open: High slew rate period is formed inside the IC (SRC2 is
good).
POL21,
POL22
Data inversion
Input
Select of inversion or no inversion for input data.
POL21: Data inversion or no inversion of Port1
POL22: Data inversion or no inversion of Port2
POL21, POL22 = H: Data are inverted in the IC.
POL21, POL22 = L: Data are not inverted in the IC.
LPC
Bias current control
Input
LPC is pulled up to the V
DD1
in the IC.
LPC = H or open: V
DD2
= 12.0 V to (13.0 V) normal static-current-consumption
mode
LPC = L: V
DD2
= (13.0 V) to 15.0 V static-current-consumption cut mode
V
0
to V
17
γ
-corrected power
supplies
Input
Input the
γ
-corrected power supplies from outside by using operational
amplifier. During the gray-scale-voltage output, be sure to keep the gray scale
level power supply at a constant level. Make sure to maintain the following
relationships.
V
DD2
−
0.2 V
≥
V
0
> V
1
> V
2
> ... ... > V
7
> V
8
≥
0.5 V
DD2
+ 0.5 V
0.5 V
DD2
−
0.5 V
≥
V
9
> V
10
> V
11
> ... ..., > V
16
> V
17
≥
0.5 V
SS2
+ 0.2 V
or
V
DD2
−
0.2 V
≥
V
8
> V
7
> V
6
> ... ... > V
1
> V
0
≥
0.5 V
DD2
+ 0.5 V
0.5 V
DD2
−
0.5 V
≥
V
17
> V
16
> V
15
> ... ... > V
10
> V
9
≥
0.5 V
SS2
+ 0.2 V
Remark
Hi-Z: High impedance
Data Sheet S16086EJ1V0DS
5
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