24LC21A
1K 2.5V Dual Mode I
2
C
™
Serial EEPROM
Features:
• Single Supply with Operation Down to 2.5V
• Completely Implements DDC1™/DDC2™
Interface for Monitor Identification, Including
Recovery to DDC1
• Pin and Function Compatible with 24LC21
• Low-Power CMOS Technology
- 1 mA typical active current
- 10
μA
standby current typical at 5.5V
• 2-Wire Serial Interface Bus, I
2
C™ Compatible
• 100 kHz (2.5V) and 400 kHz (5V) Compatibility
• Self-Timed Write Cycle (including auto-erase)
• Page Write Buffer for up to Eight Bytes
• 1,000,000 Erase/Write Cycles Ensured
• Data Retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC Package
• Available for Extended Temperature Ranges
- Industrial (I):
-40°C to +85°C
• Pb-Free and RoHS Compliant
Package Types
PDIP
NC
NC
NC
V
SS
SOIC
NC
NC
NC
Vss
1
24LC21A
2
3
4
8
7
6
5
Vcc
VCLK
SCL
SDA
1
24LC21A
2
3
4
8
7
6
5
Vcc
VCLK
SCL
SDA
Block Diagram
HV Generator
Description:
The Microchip Technology Inc. 24LC21A is a 128 x 8-bit
dual-mode Electrically Erasable PROM. This device is
designed for use in applications requiring storage and
serial transmission of configuration and control informa-
tion. Two modes of operation have been implemented:
Transmit-Only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-Only mode,
sending a serial bit stream of the memory array from 00h
to 7Fh, clocked by the VCLK pin. A valid high-to-low
transition on the SCL pin will cause the device to enter
the transition mode, and look for a valid control byte on
the I
2
C bus. If it detects a valid control byte from the
master, it will switch into Bidirectional mode, with byte
selectable read/write capability of the memory array
using SCL. If no control byte is received, the device will
revert to the Transmit-Only mode after it receives 128
consecutive VCLK pulses while the SCL pin is idle. The
24LC21A is available in a standard 8-pin PDIP and
SOIC package in industrial temperature range.
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
SDA
SCL
YDEC
VCLK
Sense AMP
R/W Control
V
CC
V
SS
Pin Function Table
Name
V
SS
SDA
SCL
VCLK
V
CC
NC
Function
Ground
Serial Address/Data I/O
Serial Clock (Bidirectional mode)
Serial Clock (Transmit-Only mode)
+2.5V to 5.5V Power Supply
No Connection
DDC is a trademark of the Video Electronics Standards
Association.
I
2
C is a trademark of Philips Corporation.
©
2008 Microchip Technology Inc.
DS21160G-page 1
24LC21A
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
.........................................................................................................................................-
0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= +2.5V to 5.5V
Industrial (I):
T
A
=-40°C to +85°C
Symbol
V
IH
V
IL
V
IH
V
IL
V
HYS
V
OL1
V
OL2
I
LI
I
LO
C
IN
, C
OUT
I
CC
Write
I
CC
Read
I
CCS
Min.
0.7 V
CC
—
2.0
—
.05 V
CC
—
—
—
—
—
—
—
—
—
Max.
—
0.3 V
CC
—
0.2 V
CC
—
0.4
0.6
±1
±1
10
3
1
30
100
Units
V
V
V
V
V
V
V
μA
μA
pF
mA
mA
μA
μA
V
CC
≥
2.7V
(Note)
V
CC
< 2.7V
(Note)
(Note)
I
OL
= 3 mA, V
CC
= 2.5V
(Note)
I
OL
= 6 mA, V
CC
= 2.5V
V
IN
= 0.1V to V
CC
V
OUT
= 0.1V to V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
V
CLK
= V
SS
Conditions
DC CHARACTERISTICS
Parameter
SCL and SDA pins:
High-level input voltage
Low-level input voltage
Input levels on VCLK pin:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note:
This parameter is periodically sampled and not 100% tested.
DS21160G-page 2
©
2008 Microchip Technology Inc.
24LC21A
TABLE 1-2:
AC CHARACTERISTICS
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Vcc = 2.5-5.5V
Standard Mode
Min.
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
Vcc = 4.5 - 5.5V
Fast Mode
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Remarks
Parameter
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
Start condition
(Note 2)
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppres- T
SP
sion (SDA and SCL pins)
Write cycle time
T
WR
Transmit-Only Mode Parameters
Output valid from VCLK
T
VAA
VCLK high time
T
VHIGH
VCLK low time
T
VLOW
VCLK setup time
T
VHST
VCLK hold time
T
SPVL
Mode transition time
T
VHZ
Transmit-only power-up
T
VPU
time
Input filter spike suppres- T
SPV
sion (VCLK pin)
Endurance
—
Note 1:
2:
3:
4:
—
—
—
—
4000
4700
0
4000
—
0
—
1M
250
50
10
2000
—
—
—
—
1000
—
100
—
20 + 0.1
C
B
—
—
—
600
1300
0
600
—
0
—
1M
250
50
10
1000
—
—
—
—
500
—
100
—
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
cycles
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1),
C
B
≤
100 pF
(Note 3)
Byte or Page mode
25°C, Vcc = 5.0V, Block
mode
(Note 4)
Not 100% tested. C
B
= Total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to Schmitt Trigger inputs which provide noise and
spike suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
©
2008 Microchip Technology Inc.
DS21160G-page 3
24LC21A
2.0
FUNCTIONAL DESCRIPTION
The 24LC21A is designed to comply to the DDC
Standard proposed by VESA (Figure 3-3) with the
exception that it is not Access.bus capable. It operates
in two modes, the Transmit-Only mode and the
Bidirectional mode. There is a separate 2-wire protocol
to support each mode, each having a separate clock
input but sharing a common data line (SDA). The
device enters the Transmit-Only mode upon power-up.
In this mode, the device transmits data bits on the SDA
pin in response to a clock signal on the VCLK pin. The
device will remain in this mode until a valid high-to-low
transition is placed on the SCL input. When a valid
transition on SCL is recognized, the device will switch
into the Bidirectional mode and look for its control byte
to be sent by the master. If it detects its control byte, it
will stay in the Bidirectional mode. Otherwise, it will
revert to the Transmit-Only mode after it sees 128
VCLK pulses.
it be initialized prior to valid data being sent in the
Transmit-Only mode (Section
2.2 “Initialization Pro-
cedure”).
In this mode, data is transmitted on the SDA
pin in 8-bit bytes, with each byte followed by a ninth,
null bit (Figure 2-1). The clock source for the Transmit-
Only mode is provided on the VCLK pin, and a data bit
is output on the rising edge on this pin. The eight bits in
each byte are transmitted Most Significant bit first.
Each byte within the memory array will be output in
sequence. After address 7Fh in the memory array is
transmitted, the internal Address Pointers will wrap
around to the first memory location (00h) and continue.
The Bidirectional mode Clock (SCL) pin must be held
high for the device to remain in the Transmit-Only
mode.
2.2
Initialization Procedure
2.1
Transmit-Only Mode
The device will power-up in the Transmit-Only mode at
address 00h. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
contents of the memory array. This device requires that
After V
CC
has stabilized, the device will be in the Trans-
mit-Only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit in address
00h. (Figure 2-2).
FIGURE 2-1:
SCL
TRANSMIT-ONLY MODE
Tvaa
SDA
Tvaa
Null Bit
Bit 1 (LSB)
Bit 1 (MSB)
Bit 7
VCLK
Tvhigh Tvlow
FIGURE 2-2:
Vcc
SCL
DEVICE INITIALIZATION
Tvaa
High-Impedance for 9 Clock Cycles
Tvpu
Tvaa
Bit 8
Bit 7
SDA
VCLK
1
2
8
9
10
11
DS21160G-page 4
©
2008 Microchip Technology Inc.
24LC21A
3.0
BIDIRECTIONAL MODE
Before the 24LC21A can be switched into the
Bidirectional mode (Figure 3-1), it must enter the
Transition mode, which is done by applying a valid
high-to-low transition on the Bidirectional mode clock
(SCL). As soon it enters the Transition mode, it looks
for a control byte
‘1010 000X’
on the I
2
C™ bus, and
starts to count pulses on VCLK. Any high-to-low transi-
tion on the SCL line will reset the count. If it sees a
pulse count of 128 on VCLK while the SCL line is idle,
it will revert back to the Transmit-Only mode, and
transmit its contents starting with the Most Significant
bit in address 00h. However, if it detects the control
byte on the I
2
C™ bus, (Figure 3-2) it will switch to the
in the Bidirectional mode. Once the device has made
the transition to the Bidirectional mode, the only way to
switch the device back to the Transmit-Only mode is to
remove power from the device. The mode transition
process is shown in detail in Figure 3-3.
Once the device has switched into the Bidirectional
mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two-wire
Bidirectional data transmission protocol (I
2
C™). In this
protocol, a device that sends data on the bus is defined
to be the transmitter, and a device that receives data
from the bus is defined to be the receiver. The bus must
be controlled by a master device that generates the
Bidirectional mode clock (SCL), controls access to the
bus and generates the Start and Stop conditions, while
the 24LC21A acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated. In the
Bidirectional mode, the 24LC21A only responds to
commands for device
‘1010 000X’.
FIGURE 3-1:
MODE
SCL
MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
Transmit-Only
Bidirectional
TVHZ
Recovery to Transmit-Only mode
(MSB of data in 00h)
SDA
VCLK count =
VCLK
1
2
3
4
127 128
Bit 8
FIGURE 3-2:
SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE
Transition mode with possibility to return to Transmit-Only mode
Bidirectional
permanently
Transmit-Only
MODE
SCL
SDA
VCLK count =
VCLK
1
2
n
S
1
0
0
1
0
0
0
0
0
ACK
n < 128
©
2008 Microchip Technology Inc.
DS21160G-page 5
京公网安备 11010802033920号
EEWORLD
