MEMS based HCSL, LVDS, LVPECL Oscillator
Data Sheet
VM-702
VM-702
Description
Vectron’s VM-702 is a silicon based MEMS stabilized, differential output oscillator, operating off a 2.5 or 3.3 volt supply in a
hermetically sealed 5x7 plastic package.
Features
•
•
•
•
•
•
10.00-460.0000MHz Output Frequencies
Low Power
Differential Output
Enable/Disable
2.25V to 3.6V Operation
-20/70°C or -40/85°C Operation
•
•
•
•
•
•
•
•
•
•
Applications
PCI Express
Ethernet, GbE, Synchronous Ethernet
Fiber Channel
Enterprise Servers
Telecom
Driving FPGA’s
Test and Measurement
PON
Medical
COTS
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
Complementary
Output
Output
V
DD
MEMS
Oscillator
& Temp Comp
PLL
E/D
NC
GND
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page1
Performance Specifications
Table 1. Electrical Performance, HCSL Output
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
Stability
2
(Ordering Options)
Outputs
Output Logic Levels
Output Logic High
Output Logic Low
Output Rise and Fall Time
3
Rise Time
Fall Time
Load
Duty Cycle
4
Jitter (200 kHz - 20 MHz ) 156.250MHz
5
12kHz-20MHz
Period Jitter
6
RMS
P/P
Output Enabled
7
Output Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
фJ
фJ
3.9
28
Enable/Disable
V
IH
V
IL
t
D
I
E/D
t
SU
T
OP
-10/70 or -40/85
5.0 x 7.0 x 0.9
0.75*V
DD
0.25*V
DD
5
±200
5
V
V
ns
uA
ms
°C
mm
ps
ps
48
280
1.7
V
OH
V
OL
t
R
t
F
50 ohms to ground
52
%
fs
ps
0.725
0.1
400
400
V
V
ps
ps
Symbol
V
DD
I
DD
Min
Supply
2.25
Frequency
Typical
Maximum
3.60
42
Units
V
mA
MHz
ppm
f
N
10
±10, ±25, ±50
460
1. The VM-702 power supply pin should be filtered, e.g., a 0.1 and 0.01uf capacitor.
2. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
3. Figure 1 defines the test circuit and Figure 2 defines these parameters.
4. Duty Cycle is defined as the On Time/Period.
5. Measured using an Agilent E5052.
6. Measured using a Wavecrest SIA3300C, 90K samples.
7. Outputs will be Enabled if the Enable/Disable pad is left open.
t
R
1
2
3
6
5
4
50 Ω
50 Ω
t
F
V
AMP
*0.8
Cross Point
V
AMP
*0.2
On Time
Period
Figure 2.
V
AMP
Figure 1.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Performance Specifications
Table 2. Electrical Performance, LVPECL Option
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
Stability
,3
(Ordering Option)
Outputs
Output Logic Levels
4
Output Logic High
Output Logic Low
Output Rise and Fall Time
3
Load
Duty Cycle
4
Jitter, 156.250MHz
5
200kHz-20MHz
12kHz -20MHz
Period Jitter
6
RMS
P/P
Output Enabled
7
Output Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
t
SU
T
OP
-10/70 or -40/85
5.0 x 7.0 x 0.9
фJ
280
1.7
фJ
3.9
28
Enable/Disable
V
IH
V
IL
t
D
0.75*V
DD
0.25*V
DD
5
±200
5
V
V
ns
uA
ms
°C
mm
ps
ps
fs
ps
48
V
OH
V
OL
t
R
/t
F
50 ohms into V
DD
-1.3V
52
%
V
DD
-1.08
V
DD
-1.555
V
V
ps
Symbol
V
DD
I
DD
Min
Supply
2.25
Frequency
Typical
Maximum
3.60
32
Units
V
mA
MHz
ppm
f
N
10
±10, ±25, ±50
460
1. The VM-702 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
3. Figure 3 defines the test circuit and Figure 4 defines these parameters.
4. Duty Cycle is defined as the On/Time Period.
5. Measured using an Agilent E5052.
6. Measured using a Wavecrest SIA3300C, 90K samples.
7. Outputs will be Enabled if Enable/Disable is left open.
V
DD
-1.3V
t
R
V
AMP
*0.8
Cross Point
V
AMP
*0.2
t
F
1
NC
2
NC
3
6
5
4
V
AMP
On Time
50
-1.3V
50
Period
Figure 3.
Figure 4.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Performance Specifications
Table 3. Electrical Performance, LVDS Option
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
Stability
2
(Ordering Option)
Outputs
Output Logic Levels
3
Output Logic High
Output Logic Low
Differential Output Amplitude
Differential Output Error
Offset Voltage
Offset Voltage Error
Output Leakage Current
Output Rise and Fall Time
3
Load
Duty Cycle
4
Jitter, 156.250MHz
5
200kHz -2 0MHz
12kHz - 20MHz
Period Jitter
6
RMS
P/P
Output Enabled
7
Output Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
фJ
280
1.7
фJ
3.9
28
Enable/Disable
V
IH
V
IL
t
D
I
E/D
t
SU
T
OP
-10/70 or -40/85
5.0 x 7.0 x 0.9
0.75*V
DD
0.25*V
DD
5
±200
5
V
V
ns
uA
ms
°C
mm
ps
ps
fs
ps
48
t
R
/t
F
100 ohms differential
50
52
%
1.125
1.25
V
OH
V
OL
1.43
1.10
350
1.6
450
50
1.4
50
10
400
V
V
mV
mV
V
mV
uA
ps
Symbol
V
DD
I
DD
Min
Supply
2.25
Typical
Maximum
3.60
60
Units
V
V
mA
MHz
ppm
Frequency
f
N
10
±10, ±25, ±50
460
0.9
250
1. The VM-702 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
3. Figure 5 defines these parameters and Figure 4 defines the test circuit.
4. Duty Cycle is defined as the On/Time Period.
5. Measured using an Agilent E5052.
6. Measured using a Wavecrest SIA3300C, 90K samples.
7. Outputs will be Enabled if Enable/Disable is left open.
Out
50
50
Out
0.01 uF
DC
6
1
5
2
4
3
Figure 5.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page4
Package and Pinout
Table 4. Pinout
Pin #
1
2
3
4
5
6
Symbol
E/D or NC
NC
GND
f
O
Cf
O
V
DD
Function
Enable/Disable
No Connection
Electrical and Lid Ground
Output Frequency
Complementary Output Frequency
Supply Voltage
Contact Pads are
Gold flash (0.003 um min ) over
Palladium (0.01-0.15um) over
Nickel (0.508-2.032um)
7.0±0.10 [0.276±0.004]
2.54 [1.00]
1.4±0.10 [0..055±0.004]
1.1±0.10 [0.043±0.004]
Power Supply cap
is required
Via to Supply
Via to GND
5.0±0.10 [0.197±0.004]
3.7 [0.148]
2.8 [1.10]
0.85±0.05 [0.033±0.002]
Dimensions are in mm
Figure 6. Package Outline Drawing
Figure 7. Pad Layout
HCSL Application Diagrams
15mA
1
2
3
6
5
4
50 Ω
Z
L
=50 ohms
Z
L
=50 ohms
50 Ω
1
2
3
6
10-30 Ω
5
10-30 Ω
4
50 Ω
Z
L
=50 ohms
50 Ω
Z
L
=50 ohms
Figure 8.
Standard HCSL Output Configuration
Figure 9.
Single Resistor Termination Scheme
Figure 10.
In some cases a 10-30 ohm series resistor is
used to help reduce overshoot.
The VM-702 incorporates a standard High Speed Current Logic, HCSL ,output scheme which is a 15mA current source switched between Out and Comple-
mentary Out. Being un-terminated drains, as shown in Figure 8, they require external 50 ohm resistors to ground as shown in Figure 9. HCSL is a high im-
pedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor as shown in Figure 10, to help reduce overshoot/
ringing.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page5
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