IS66WVD409616ALL
Advanced Information
64Mb Async and Burst CellularRAM 2.0
Overview
The IS66WVD409616ALL is an integrated memory device containing 64Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device uses a
multiplexed address and data bus scheme to minimize pins and includes a industry standard burst
mode for increased read and write bandwidth. The device includes several power saving modes :
Reduced Array Refresh mode where data is retained in a portion of the array and Temperature
Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a
standard asynchronous mode and high performance burst mode. The die has separate power rails,
VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Single device supports asynchronous and burst
operation
Mixed Mode supports asynchronous write and
synchronous read operation
Dual voltage rails for optional performance
VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Multiplexed address and data bus
ADQ0~ADQ15
Asynchronous mode read access : 70ns
Burst mode for Read and Write operation
4, 8, 16 or Continuous
Low Power Consumption
Asynchronous Operation < 25 mA
Burst operation < 45 mA (@133Mhz)
Standby < 140 uA(max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Reduced Array Refresh
Temperature Controlled Refresh
Operation Frequency up to 133MHz
Operating temperature Range
Industrial -40°C~85°C
Package: 54-ball VFBGA
Copyright © 2009 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
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IS66WVD409616ALL
Advanced Information
General Description
CellularRAM™ (Trademark of MicronTechnology) products are high-speed, CMOS pseudo-static
random access memories developed for low-power, portable applications.
The 64Mb DRAM core device is organized as 4 Meg x 16 bits. This device is a variation
of the industry-standard Flash control interface, with a multiplexed address/data bus.
The multiplexed address and data functionality dramatically reduce the required
signal count, and increase READ/WRITE bandwidth.
To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a
transparent self-refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices.
The refresh configuration register (RCR) is used to control how refresh is performed on
the DRAM array. These registers are automatically loaded with default settings during
power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three mechanisms to minimize standby current. Partial
array refresh (PAR) enables the system to limit refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) uses an
on-chip sensor to adjust the refresh rate to match the device temperature — the refresh
rate decreases at lower temperatures to minimize current consumption during standby.
Deep power-down (DPD) enables the system to halt the refresh operation altogether
when no vital information is stored in the device. The system-configurable refresh
mechanisms are adjusted through the RCR.
This CellularRAM device is compliant with the industry-standard CellularRAM 2.0
feature set established by the CellularRAM Workgroup. It includes support for both
variable and fixed latency, with three drive strengths, a variety of wrap options, and a
device ID register (DIDR).
A16~A21
Address
Decode Logic
Refresh
Configuration Register
(RCR)
Device ID Register
(DIDR)
Bus
Configuration Register
(BCR)
4096K X 16
DRAM
Memory Array
Input
/Output
Mux
And
Buffers
CE#
WE#
OE#
CLK
ADV#
CRE
LB#
UB#
WAIT
Control
Logic
ADQ0~ADQ15
[ Functional Block Diagram]
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Rev.00A | January 2010
IS66WVD409616ALL
Advanced Information
54Ball VFBGA Ball Assignment
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
LB#
ADQ8
ADQ9
VSSQ
VDDQ
ADQ14
ADQ15
A18
WAIT
OE#
UB#
ADQ10
ADQ11
ADQ12
ADQ13
A19
NC
CLK
NC
NC
NC
A17
A21
NC
NC
NC
ADV#
NC
NC
NC
NC
A16
NC
NC
NC
NC
NC
CE#
ADQ1
ADQ3
ADQ4
ADQ5
WE#
NC
NC
CRE
ADQ0
ADQ2
VDD
VSS
ADQ6
ADQ7
A20
NC
[Top View]
(Ball Down)
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IS66WVD409616ALL
Advanced Information
Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VDD
VDDQ
VSS
VSSQ
ADQ0~
ADQ15
A16~A21
LB#
UB#
CE#
OE#
WE#
CRE
ADV#
Type
Power Supply
Power Supply
Power Supply
Power Supply
Input / Output
Input
Input
Input
Input
Input
Input
Input
Input
Description
Core Power supply (1.7V~1.95V)
I/O Power supply (1.7V~1.95V)
All VSS supply pins must be connected to Ground
All VSSQ supply pins must be connected to Ground
Address Input(A0~A15)
Data Input/Output (DQ0~DQ15)
Address Input(A16~A21)
Lower Byte select
Upper Byte select
Chip Enable/Select
Output Enable
Write Enable
Control Register Enable: When CRE is HIGH, READ and WRITE operations
access registers.
Address Valid signal
Signal that a valid address is present on the address bus. Address are
latched on the rising edge of ADV# during asynchronous Read/Write
operations. Addresses are latched on the rising edge of CLK with ADV#
low during synchronous operation.
Clock
Latches addresses and commands on the first rising CLK edge when
ADV# is active in synchronous mode. CLK must be kept static Low during
asynchronous Read/Write operations.
WAIT
Data valid signal during burst Read/Write operation. WAIT is used to
arbitrate collisions between refresh and Read/Write operation. WAIT is
also asserted at the end of a row unless wrapping within the burst length.
WAIT is asserted and should be ignored during asynchronous READ
operation. WAIT is gated by CE# and is high-Z when CE# is high.
CLK
Input
WAIT
Output
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IS66WVD409616ALL
Advanced Information
Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
Mode
Power
CLK
1
ADV#
CE#
OE#
WE#
CRE
2
UB#/
LB#
WAIT
3
ADQ
[15:0]
4
Note
Asynchronous Mode
Read
Write
Standby
No Operation
Configuration
Register Write
Configuration
Register Read
Deep Power-
Down
Active
Active
Stand
by
Idle
Active
Active
DPD
L
L
L
L
L
L
L
X
X
X
L
L
H
L
L
L
H
L
X
X
X
H
L
X
H
L
X
X
L
H
X
L
L
L
L
H
H
X
L
L
X
X
X
L
X
Low-Z
High-Z
High-Z
Low-Z
High-Z
Low-Z
High-Z
Data-out
Data-in
High-Z
X
High-Z
Config-Reg
Out
High-Z
10
5
5
6,7
5,7
Synchronous Mode (Burst Mode)
Async read
Async write
Standby
No operation
Initial
burst read
Initial
burst write
Burst
continue
Burst suspend
Configuration
register write
Configuration
register read
Deep Power-
Down
Active
Active
Stand
by
Idle
Active
Active
Active
Active
Active
Active
DPD
L
L
L
L
L
L
X
X
L
L
H
L
L
L
X
L
L
H
L
L
L
L
L
L
L
H
L
X
X
X
X
H
X
H
H
L
X
H
L
X
X
H
L
X
X
L
H
X
L
L
L
L
L
L
L
L
H
H
X
L
L
X
X
L
X
L
X
X
L
X
Low-Z
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
High-Z
Data-Out
Data-In
High-Z
X
Address
Address
Data-In or
Data-Out
High-Z
High-Z
Config-Reg
Out
High-Z
5
5
6,7
5,8
5,8
5,8
5,8
5,8
8,11
8,11
10
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