IS66WVD409616ALL-7013BLI datasheet, PDF

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IS66WVD409616ALL-7013BLI: DescriptionPseudo Static RAM, 4MX16, 70ns, CMOS, PBGA54, 8 X 6 MM, MO-207, VFBGA-54; Categorystorage storage; File Size1MB，52 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS66WVD409616ALL-7013BLI Overview

Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA54, 8 X 6 MM, MO-207, VFBGA-54

IS66WVD409616ALL-7013BLI Parametric

Parameter Name	Attribute value
Maker	Integrated Silicon Solution ( ISSI )
package instruction	VFBGA,
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	70 ns
JESD-30 code	R-PBGA-B54
length	8 mm
memory density	67108864 bit
Memory IC Type	PSEUDO STATIC RAM
memory width	16
Number of functions	1
Number of terminals	54
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
width	6 mm
Base Number Matches	1

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IS66WVD409616ALL

Advanced Information

64Mb Async and Burst CellularRAM 2.0

Overview

The IS66WVD409616ALL is an integrated memory device containing 64Mbit Pseudo Static Random

Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device uses a

multiplexed address and data bus scheme to minimize pins and includes a industry standard burst

mode for increased read and write bandwidth. The device includes several power saving modes :

Reduced Array Refresh mode where data is retained in a portion of the array and Temperature

Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a

standard asynchronous mode and high performance burst mode. The die has separate power rails,

VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.

Features

Single device supports asynchronous and burst

operation

Mixed Mode supports asynchronous write and

synchronous read operation

Dual voltage rails for optional performance

VDD 1.7V~1.95V, VDDQ 1.7V~1.95V

Multiplexed address and data bus

ADQ0~ADQ15

Asynchronous mode read access : 70ns

Burst mode for Read and Write operation

4, 8, 16 or Continuous

Low Power Consumption

Asynchronous Operation < 25 mA

Burst operation < 45 mA (@133Mhz)

Standby < 140 uA(max.)

Deep power-down (DPD) < 3uA (Typ)

Low Power Feature

Reduced Array Refresh

Temperature Controlled Refresh

Operation Frequency up to 133MHz

Operating temperature Range

Industrial -40°C~85°C

Package: 54-ball VFBGA

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

Rev.00A | January 2010

www.issi.com

- SRAM@issi.com

IS66WVD409616ALL

Advanced Information

General Description

CellularRAM™ (Trademark of MicronTechnology) products are high-speed, CMOS pseudo-static

random access memories developed for low-power, portable applications.

The 64Mb DRAM core device is organized as 4 Meg x 16 bits. This device is a variation

of the industry-standard Flash control interface, with a multiplexed address/data bus.

The multiplexed address and data functionality dramatically reduce the required

signal count, and increase READ/WRITE bandwidth.

To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a

transparent self-refresh mechanism. The hidden refresh requires no additional support

from the system memory controller and has no significant impact on device read/write

performance.

Two user-accessible control registers define device operation. The bus configuration

bus and is nearly identical to its counterpart on burst mode Flash devices.

The refresh configuration register (RCR) is used to control how refresh is performed on

the DRAM array. These registers are automatically loaded with default settings during

power-up and can be updated anytime during normal operation.

Special attention has been focused on standby current consumption during self refresh.

CellularRAM products include three mechanisms to minimize standby current. Partial

array refresh (PAR) enables the system to limit refresh to only that part of the DRAM

array that contains essential data. Temperature-compensated refresh (TCR) uses an

on-chip sensor to adjust the refresh rate to match the device temperature — the refresh

rate decreases at lower temperatures to minimize current consumption during standby.

Deep power-down (DPD) enables the system to halt the refresh operation altogether

when no vital information is stored in the device. The system-configurable refresh

mechanisms are adjusted through the RCR.

This CellularRAM device is compliant with the industry-standard CellularRAM 2.0

feature set established by the CellularRAM Workgroup. It includes support for both

variable and fixed latency, with three drive strengths, a variety of wrap options, and a

device ID register (DIDR).

A16~A21

Address

Decode Logic

Refresh

Configuration Register

(RCR)

Device ID Register

(DIDR)

Bus

Configuration Register

(BCR)

4096K X 16

DRAM

Memory Array

Input

/Output

Mux

And

Buffers

CE#

WE#

OE#

CLK

ADV#

CRE

LB#

UB#

WAIT

Control

Logic

ADQ0~ADQ15

[ Functional Block Diagram]

www.issi.com

- SRAM@issi.com

Rev.00A | January 2010

IS66WVD409616ALL-7013BLI Related Products

	IS66WVD409616ALL-7013BLI	IS66WVD409616ALL-7010BLI	IS66WVD409616ALL-7008BLI
Description	Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA54, 8 X 6 MM, MO-207, VFBGA-54	Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA54, 8 X 6 MM, MO-207, VFBGA-54	Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA54, 8 X 6 MM, MO-207, VFBGA-54
package instruction	VFBGA,	VFBGA,	VFBGA,
Reach Compliance Code	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	70 ns	70 ns	70 ns
JESD-30 code	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54
length	8 mm	8 mm	8 mm
memory density	67108864 bit	67108864 bit	67108864 bit
Memory IC Type	PSEUDO STATIC RAM	PSEUDO STATIC RAM	PSEUDO STATIC RAM
memory width	16	16	16
Number of functions	1	1	1
Number of terminals	54	54	54
word count	4194304 words	4194304 words	4194304 words
character code	4000000	4000000	4000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
organize	4MX16	4MX16	4MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA	VFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm	1 mm
Maximum supply voltage (Vsup)	1.95 V	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL
Terminal pitch	0.75 mm	0.75 mm	0.75 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	6 mm	6 mm	6 mm
Base Number Matches	1	1	1

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