VCC1
CMOS Crystal Oscillator
VCC1
Description
Vectron’s VCC1 Crystal Oscillator (XO) is a quartz stabilized square wave generator with a CMOS output. The VCC1 uses a fundamental or 3rd
overtone crystal resulting in very low jitter performance, and a monolithic IC which improves reliability and reduces cost.
Features
•
•
•
•
•
•
•
•
•
Applications
•
•
•
•
•
•
•
•
•
•
SONET/SDH/DWDM
Ethernet, GE, SynchE
Storage Area Networking
Fiber Channel
Digital Video
Broadband Access
Base Stations, Picocells
Driving A/D’s, D/A’s, FPGA’s
Test and Measurement
COTS
Ultra Low Jitter, Fundamental or 3rd OT Crystal Design
CMOS Output Crystal Oscillator
Output Frequencies from 1.024 MHz to 190.000 MHz
5.0, 3.3, 2.5 or 1.8 V Operation
Output Disable Feature
Excellent 20ppm temperature stability
-10/70°C , -40/85°C or -55/125°C operating temperature
Small Industry Standard Package, 5x7mm
Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
V
DD
Output
Crystal
Oscillator
E/D
Page1
GND
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Table 1. Electrical Performance, 5V Option
Parameter
Voltage
1
Max Voltage
Current
2
≤20.000MHz
20.001 to 50.000MHz
50.001 to 85.000MHz
85.001 to 125.000MHz
Current, Output Disabled
Performance Speci cations
Symbol
V
DD
I
DD
10
30
50
60
30
Frequency
f
N
1.544
Outputs
125.000
±20, ±25, ±32, ±50, ±100
uA
MHz
ppm
Minimum
Supply
4.5
-0.7
Typical
5.0
Maximum
5.5
7
Units
V
V
mA
Nominal Frequency
3
Stability
4
, (Ordering Option)
Output Logic Levels
2
Output Logic High
Output Logic Low
Output Logic High Drive
Output Logic Low Drive
Load
Output Rise /Fall Time
2
<20.000MHz
20.000 to 50.000MHz
50.001 to 125.000MHz
Output Leakage, Output Disabled
Duty Cycle
2,5
Period Jitter
6
RMS
Peak-Peak
RMS Jitter, 12k-20MHz
Output Enable/Disable
7
Output Enable
Output Disable
Disable time
Enable Internal Pull-Up Resistor
Start-Up Time
Operating Temp, (Ordering Option)
1]
2]
3]
4]
5]
6]
7]
V
OH
V
OL
I
OH
I
OL
I
OUT
t
R
/t
F
0.9*V
DD
0.1*V
DD
16
16
15
8
5
2
V
V
mA
mA
pF
ns
I
Z
45
фJ
2.5
18
фJ
Enable/Disable
V
IH
V
IL
t
D
100
t
SU
T
OP
-10/70, -40/85, -55/125
4.0
0.5
50
±10
55
uA
%
ps
1
ps
0.8
100
10
V
V
ns
Kohm
ms
°C
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for example 0.1 and 0.01uF
Parameters are tested with the test circuit shown in Figure 1.
See Standard Frequencies and Ordering Information tables for more speci c information
Includes initial accuracy, operating temperature, supply voltage, shock and vibration (not under operation) and 10 years aging.
Duty Cycle is measured as On Time/Period, see Fig 2.
Broadband Period Jitter measured using a LeCroy Wavemaster 8600A, 90K samples, see Application Note for Typical Phase Noise and Jitter Performance
The Output is Enabled if the Enable/Disable is left open.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Table 2. Electrical Performance, 3.3V Option
Parameter
Voltage
1
Maximum Voltage
Current
2
≤20.000
20.001 to 50.000
50.001 to 85.000
85.001 to 190.000
Current, Output Disabled
I
DD
Performance Speci cations
Symbol
V
DD
Mininum
Supply
2.97
-0.5
Typical
3.3
Maximum
3.63
5
7
20
30
50
30
Units
V
V
mA
uA
MHz
ppm
Frequency
Nominal Frequency
3
Stability
4
, (Ordering Option)
Outputs
Output Logic Levels
2
Output Logic High
Output Logic Low
Output Logic High Drive
Output Logic Low Drive
Load
Output Rise /Fall Time
2
<20.000MHz
20.000 to 50.000MHz
50.001 to 90.000MHz
90.001 to 190.000MHz
Output Leakage, Output Disabled
2,5
Duty Cycle
2,5
Period Jitter
6
RMS
Peak-Peak
RMS Jitter, 12k-20M
Output Enable/Disable
7
Output Enable
Output Disable
Disable time
Enable Internal Pull-Up Resistor
Start-Up Time
Operating Temp, (Ordering Option)
1]
2]
3]
4]
5]
6]
7]
f
N
1.544
190.000
±20, ±25, ±32, ±50, ±100
V
OH
V
OL
I
OH
I
OL
I
OUT
t
R
/t
F
0.9*V
DD
0.1*V
DD
8
8
15
6
4
3
2
V
V
mA
mA
pF
ns
I
Z
45
фJ
2.5
18
фJ
Enable/Disable
V
IH
V
IL
t
D
100
t
SU
T
OP
-10/70, -40/85, -55/125
2.0
0.5
50
±10
55
uA
%
ps
1
ps
0.5
100
10
V
V
ns
Kohm
ms
°C
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for example 0.1 and 0.01uF
Parameters are tested with the test circuit shown in Figure 1.
See Standard Frequencies and Ordering Information tables for more speci c information
Includes initial accuracy, operating temperature, supply voltage, shock and vibration (not under operation) and 10 years aging.
Duty Cycle is measured as On Time/Period, see Fig 2.
Broadband Period Jitter measured using a LeCroy Wavemaster 8600A, 90K samples, see Application Note for Typical Phase Noise and Jitter Performance
The Output is Enabled if the Enable/Disable is left open.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Performance Speci
Table 3. Electrical Performance, 2.5V Option
Parameter
Voltage1
Maximum Voltage
Current
2
≤20.000MHz
20.001 to 50.000MHz
50.001 to 110.000MHz
110.001 to 190.000MHz
Current, Output Disabled
Frequency
Nominal Frequency
3
Stability
4
,
(Ordering
Option)
Outputs
Output Logic Levels
2,3
Output Logic High
Output Logic Low
Output Logic High Drive
Output Logic Low Drive
Output Logic High Drive
5
Output Logic Low Drive
5
Load
Output Rise /Fall Time
2
<20.000MHz
20.000 to 50.000MHz
50.001 to 90.000MHz
90.001 to 190.000MHz
Output Leakage, Output Disabled
Duty Cycle
2,6
Period Jitter
7
RMS
Peak-Peak
RMS Jitter, 12k-20MHz
Output Enable/Disable
8
Output Enable
Output Disable
Disable time
Enable Internal Pull-Up Resistor
Start-Up Time
Operating Temp, (Ordering Option)
1]
2]
3]
4]
5]
6]
7]
cations
Typical
2.5
Symbol
V
DD
I
DD
Mininum
Supply
2.25
-0.5
Maximum
2.75
5
7
15
20
30
30
Units
V
V
mA
uA
MHz
ppm
f
N
1.544
190.000
±20, ±25, ±32, ±50, ±100
0.9*V
DD
0.1*V
DD
V
OH
V
OL
I
OH
I
OL
I
OUT
t
R
/t
F
10
6
3
2
±10
45
фJ
2.5
18
фJ
Enable/Disable
V
IH
V
IL
t
D
100
t
SU
T
OP
-10/70, -40/85, -55/125
10
1.75
0.5
100
0.5
1
50
55
4
4
8
8
15
V
V
mA
mA
mA
mA
pF
ns
uA
%
ps
ps
V
V
ns
Kohm
ms
°C
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for example 0.1 and 0.01uF
Parameters are tested with the test circuit shown in Figure 1.
See Standard Frequencies and Ordering Information tables for more speci c information
Includes initial accuracy, operating temperature, supply voltage, shock and vibration (not under operation) and 10 years aging.
Duty Cycle is measured as On Time/Period, see Fig 2.
Broadband Period Jitter measured using a LeCroy Wavemaster 8600A, 90K samples, see Application Note for Typical Phase Noise and Jitter Performance
The Output is Enabled if the Enable/Disable is left open.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page4
Table 4. Electrical Performance, 1.8V Option
Parameter
Voltage
1
Maximum Voltage
Current
2
≤20.000MHz
20.001 to 70.000MHz
70.001 to 96.000MHz
96.001 to 125.000MHz
125.001 to 172.000MHz
Current, Output Disabled
I
DD
Performance Speci cations
Symbol
V
DD
Mininum
Supply
1.71
-0.5
Typical
1.8
Maximum
1.89
3.6
5
15
20
25
30
30
Units
V
V
mA
uA
MHz
ppm
Frequency
Nominal Frequency
3
Stability
4
, (Ordering Option)
Outputs
Output Logic Levels
2,3
Output Logic High
Output Logic Low
Output Logic High Drive
Output Logic Low Drive
Output Logic High Drive
5
Output Logic Low Drive
5
Load
Output Rise /Fall Time
2
<20.000MHz
20.000 to 50.000MHz
50.001 to 90.000MHz
90.000 to 172.000MHz
Output Leakage, Output Disabled
Duty Cycle
2,6
Period Jitter
7
RMS
Peak-{eak
RMS Jitter, 12kHz-20MHz
Output Enable/Disable
8
Output Enable
Output Disable
Disable time
Enable Internal Pull-Up Resistor
Start-Up Time
Operating Temp, Ordering Option
1]
2]
3]
4]
5]
6]
7]
f
N
1.544
172.000
±20, ±25, ±32, ±50, ±100
V
OH
V
OL
I
OH
I
OL
I
OH
I
OL
I
OUT
t
R
/t
F
0.9*V
DD
0.1*V
DD
2.8
2.8
8
8
15
4
4
3
2
V
V
mA
mA
pF
ns
I
Z
45
фJ
2.5
18
фJ
Enable/Disable
V
IH
V
IL
t
D
1
t
SU
T
OP
-10/70, -40/85, -55/125
1.26
0.5
50
±10
55
uA
%
ps
1
ps
0.5
100
10
V
V
ns
Mohm
ms
°C
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for example 0.1 and 0.01uF
Parameters are tested with the test circuit shown in Figure 1.
See Standard Frequencies and Ordering Information tables for more speci c information
Includes initial accuracy, operating temperature, supply voltage, shock and vibration (not under operation) and 10 years aging.
Duty Cycle is measured as On Time/Period, see Fig 2.
Broadband Period Jitter measured using a LeCroy Wavemaster 8600A, 90K samples, see Application Note for Typical Phase Noise and Jitter Performance
The Output is Enabled if the Enable/Disable is left open.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
