4 Megabit High Speed CMOS SRAM
DPS128C32BV3
DESCRIPTION:
The DPS128C32BV3 ‘’VERSA-STACK’’ module is a
revolutionary new high speed memory subsystem using
Dense-Pac Microsystems’ ceramic Stackable Leadless Chip
Carriers (SLCC) mounted on a co-fired ceramic substrate.
It offers 4 Megabits of SRAM in a package envelope of
1.090 x 1.090 x 0.300 inches.
The DPS128C32BV3 contains four individual 128K x 8
SRAMs, packaged in their own hermetically sealed SLCCs
making the module suitable for commercial, industrial and
military applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers
a higher board density of memory than available with
conventional through-hole, surface mount, module, or
hybrid techniques.
FEATURES:
•
Organizations Available:
128K x 32, 256K x 16, or
512K x 8
•
Access Times:
20, 25, 30, 35, 45ns
•
Fully Static Operation
- No clock or refresh required
•
Single +5V Power Supply,
±10%
Tolerance
•
TTL Compatible
•
Common Data Inputs
and Outputs
•
Low Data Retention Voltage:
2.0V min.
•
66-Pin PGA ‘’VERSA-STACK’’
Package
*
Commercial only.
FUNCTIONAL BLOCK DIAGRAM
PIN-OUT DIAGRAM
PIN NAMES
A0 - A16
I/O0 - I/O31
CE0 - CE3
WE0 - WE3
OE
V
DD
V
SS
N.C.
Address Inputs
Data Input/Output
Chip Enables
Write Enables
Output Enable
Power (+5V)
Ground
No Connect
30A044-28
REV. F
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change products or specifications herein without prior notice.
1
DPS128C32BV3
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
M/B -55 +25 +125
Operating
o
T
A
C
I
-40 +25
+85
Temperature
C
0 +25
+70
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
H
L
L
L
Dense-Pac Microsystems, Inc.
TRUTH TABLE
CE
WE
X
H
H
L
L = LOW
OE
X
H
L
X
Supply
I/O Pin Current
High-Z Standby
High-Z Active
D
OUT
Active
D
IN
Active
X = Don’t Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4
V
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Storage Temperature
Temperature Under Bias
Supply Voltage
1
Input/Output Voltage
1
3
CAPACITANCE
4
: T
A
= 25
°
C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
50
20
50
50
30
Unit
pF
Condition
V
IN2
= 0V
Value
Unit
-65 to +150
°C
-55 to +125
°C
-0.5 to +7.0
°C
-0.5 to V
DD
+0.5 V
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current (CMOS)
Standby Current (TTL)
Data Retention
Supply Current (3V)
Data Retention
Supply Current (2V)
Output Low Voltage
Output High Voltage
o
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
X8
Cycle=min., Duty=100%,
X16
I
OUT
= 0mA
X32
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V,
CE
≥
V
DD
-0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V
V
DR
= 2V, CE
≥
V
DR
-0.2V
I
OUT
= 8.0mA
I
OUT
= -4.0mA
Typ.
(†)
-
-
175
250
400
1.6
100
0.28
0.14
-
-
C
Min.
Max.
Min.
I
Max.
Min.
M
Max.
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
-20
-10
+20
+10
230
340
560
20
120
1.6
1.0
-20
-10
+20
+10
245
350
560
20
140
2.4
1.6
-20
-10
+20
+10
265
390
640
40
140
8.0
7.2
2.4
0.4
2.4
0.4
2.4
0.4
† Typical measurements made at +25 C, Cycle = min., V
DD
= 5.0V.
2
30A044-28
REV. F
Dense-Pac Microsystems, Inc.
DPS128C32BV3
OUTPUT LOAD
Load
1
2
C
L
30pF
5pF
Parameters Measured
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
,and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
D
OUT
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
C
L
*
255Ω
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns**
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
3
0
3
20
20
8
10
8
25
3
0
3
25
25
10
12
10
30
3
0
3
30
30
15
15
15
35
3
0
3
35
35
20
20
20
45
3
0
3
45
45
25
25
25
** Available in Commercial Only.
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
: Over operating ranges
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time ***
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20ns**
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
15
0
15
0
12
0
3
8
25
20
20
0
20
0
15
0
3
10
30
25
25
0
25
0
15
0
3
12
35
30
30
0
30
0
20
0
3
15
45
40
40
0
35
0
25
0
3
20
** Available in Commercial Only.
*** Valid for both Read and Write Cycles.
30A044-28
REV. F
3
DPS128C32BV3
Dense-Pac Microsystems, Inc.
Data Retention AC Characteristics
8
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data
Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V,
V
IN
≥
V
DR
-0.2V or V
IN
≤
V
SS
+0.2V
See Data Retention Waveform
See Data Retention Waveform
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
READ CYCLE
ADDRESS
CE
OE
DATA I/O
4
30A044-28
REV. F
Dense-Pac Microsystems, Inc.
DPS128C32BV3
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-28
REV. F
5
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