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UPD780034AYGK-XXX-9ET

Description
Microcontroller, 8-Bit, MROM, 12MHz, MOS, PQFP64, 12 X 12 MM, PLASTIC, TQFP-64
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size536KB,98 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPD780034AYGK-XXX-9ET Overview

Microcontroller, 8-Bit, MROM, 12MHz, MOS, PQFP64, 12 X 12 MM, PLASTIC, TQFP-64

UPD780034AYGK-XXX-9ET Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instruction12 X 12 MM, PLASTIC, TQFP-64
Reach Compliance Codecompliant
Has ADCYES
Other featuresOPERATES AT 1.8 V MINIMUM SUPPLY @ 5 MHZ
Address bus width16
bit size8
maximum clock frequency12 MHz
DAC channelNO
DMA channelNO
External data bus width8
JESD-30 codeS-PQFP-G64
JESD-609 codee0
length12 mm
Number of I/O lines51
Number of terminals64
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeTQFP
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
ROM programmabilityMROM
Maximum seat height1.2 mm
speed12 MHz
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width12 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
Base Number Matches1
DATA SHEET
µ
PD780031A, 780032A, 780033A, 780034A
780031AY, 780032AY, 780033AY, 780034AY
8-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD780031A, 780032A, 780033A, and 780034A are members of the
µ
PD780034A Subseries of the 78K/0
Series. Only selected functions of the existing
µ
PD78054 Subseries are provided, and the serial interface is enhanced.
The
µ
PD780031AY, 780032AY, 780033AY, and 780034AY are the
µ
PD780034A Subseries with a multimaster
supporting I
2
C bus interface, which makes them suitable for AV equipment.
Flash memory versions, the
µ
PD78F0034A, 78F0034B, 78F0034AY, and 78F0034BY, that can operate in the same
power supply voltage range as the mask ROM versions, and various development tools, are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µ
PD780024A, 780034A, 780024AY, 780034AY
Subseries User’s Manual:
U14046E
78K/0 Series Instructions User’s Manual:
U12326E
FEATURES
• Internal ROM and RAM
Item
Part Number
Program Memory
(Internal ROM)
8 KB
16 KB
24 KB
32 KB
1024 bytes
Data Memory
(Internal High-Speed RAM)
512 bytes
Package
• 64-pin plastic SDIP (19.05 mm (750))
• 64-pin plastic QFP (14 x 14)
• 64-pin plastic LQFP (14 x 14)
• 64-pin plastic TQFP (12 x 12)
• 64-pin plastic LQFP (10 x 10)
• 73-pin plastic FBGA (9 x 9)
µ
PD780031A, 780031AY
µ
PD780032A, 780032AY
µ
PD780033A, 780033AY
µ
PD780034A, 780034AY
• External memory expansion space: 64 KB
• Minimum instruction execution time
• Expanded-specification products of
µ
PD780031A, 780032A, 780033A, 780034A: 0.166
µ
s (f
X
= 12 MHz, V
DD
= 4.5 to 5.5 V)
µ
PD780031AY, 780032AY, 780033AY, 780034AY and conventional products of
µ
PD780031A, 780032A,
780033A, 780034A: 0.238
µ
s (f
X
= 8.38 MHz, V
DD
= 4.0 to 5.5 V)
• I/O ports: 51 (N-ch open-drain (5 V withstanding voltage): 4)
• 10-bit resolution A/D converter: 8 channels (AV
DD
= 1.8 to 5.5 V)
• Serial interface: 3 channels
µ
PD780031A, 780032A, 780033A, 780034A: UART mode, 3-wire serial I/O mode (2 channels)
µ
PD780031AY, 780032AY, 780033AY, 780034AY: UART mode, 3-wire serial I/O mode, I
2
C bus mode
• Timer: 5 channels
• Power supply voltage: V
DD
= 1.8 to 5.5 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U14044EJ4V0DS00 (4th edition)
Date Published December 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
©
2000
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