IDTCV133PA datasheet, PDF - EEWORLD Datasheet

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IDTCV133PA: DescriptionProcessor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56; CategoryThe embedded processor and controller Microcontrollers and processors; File Size140KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

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IDTCV133PA Overview

Processor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56

IDTCV133PA Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	TSSOP
package instruction	TSSOP-56
Contacts	56
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G56
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	1
Number of terminals	56
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	400 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP56,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Master clock/crystal nominal frequency	14.31818 MHz
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum slew rate	400 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	6.1 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches	1

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IDTCV133

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC

CLOCK FOR P4 PROCESSOR

IDTCV133

FEATURES:

DESCRIPTION:

• Power management control suitable for notebook applications

• One high precision PLL for CPU, SSC and N programming

• One high precision PLL for SRC/PCI, supports 100MHz output

frequency, SSC and N programming

• One high precision PLL for LVDS. Supports 100/96MHz output

frequency, SSC programming

• One high precision PLL for 96MHz/48MHz

• Band-gap circuit for differential outputs

• Support spread spectrum modulation, –0.5 down spread and

others

• Support SMBus block read/write, index read/write

• Selectable output strength for REF

• Allows for CPU frequency to change to a slower frequency to

conserve power when an application is less execution-

intensive

• Smooth transition for N programming

• Available in TSSOP package

IDTCV133 is a 56 pin clock device, incorporating both Intel CK410M and

CKSSCD requirements, for Intel advance P4 processors. The CPU output

buffer is designed to support up to 400MHz processor. This chip has four PLLs

inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device

also implements Band-gap referenced I

REF

to reduce the impact of V

variation

on differential outputs, which can provide more robust system performance.

Each CPU/SRC/LVDS has its own Spread Spectrum selection.

OUTPUTS:

•

KEY SPECIFICATION:

2*0.7V current –mode differential CPU CLK pair

5*0.7V current –mode differential SRC CLK pair

One CPU_ITP/SRC selectable CLK pair

6*PCI, 2 free running, 33.3MHz

1*96MHz, 1*48MHz

1*REF

One 100/96 MHz differential LVDS

• CPU CLK cycle to cycle jitter < 100ps

• SRC CLK cycle to cycle jitter < 125ps

• PCI CLK cycle to cycle jitter < 500ps

FUNCTIONAL BLOCK DIAGRAM

PLL1

SSC

N Programmable

CPU[1:0]

CPU CLK

Output Buffer

Stop Logic

XTAL

Osc Amp

CPU_ITP/SRC7

REF

LVDS CLK

Output Buffer

Stop Logic

REF

ITP_EN

LVDS

SDATA

SCLK

SM Bus

Controller

PLL2

SSC

PLL3

SSC

N Programmable

TT_

WRGD

#/PD

SEL100/96#

CLKREQA#

CLKREQB#

FSA.B.C

PCI_STOP#

CPU_STOP#

Control

Logic

PLL4

SEL

100/96MHz

SRC CLK

Output Buffer

Stop Logic

SRC[5:1]

PCI[3:0], PCIF[1:0]

REF

48MHz

48MHz/96MHz

Output BUffer

DOT96

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

JANUARY 2005

DSC 6564/13

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