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IDT7005L35JI

Description
Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68
Categorystorage    storage   
File Size229KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT7005L35JI Overview

Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68

IDT7005L35JI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeLCC
package instruction0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68
Contacts68
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time35 ns
Other featuresSEMAPHORE; AUTOMATIC POWER DOWN
I/O typeCOMMON
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.2062 mm
memory density65536 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals68
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum standby current0.004 A
Minimum standby current2 V
Maximum slew rate0.25 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width24.2062 mm
Base Number Matches1
HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
Features
x
x
IDT7005S/L
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 35/55ns (max.)
– Commercial:15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7005L
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
x
x
x
x
x
x
x
x
x
x
one device
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
thin quad flatpack
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
12L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
Address
Decoder
13
(1,2)
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2738 drw 01
JUNE 1999
1
©1998 Integrated Device Technology, Inc.
DSC 2738/11
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