The VC-706 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 7. There are numerous application notes
on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 8, and a pull-up/pull-down scheme
as shown in Figure 9. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
LVDS Application Diagrams
V
CC
LVDS
Driver
100
LVDS
Receiver
LVDS
Driver
100
Receiver
OUT+
OUT-
Figure 11 LVDS to LVDS Connection, Internal 100ohm
Some LVDS structures have an internal 100 ohm resistor
on the input and do not need additional components.
Figure 10 Standard LVDS
Output Configuration
Figure 12 LVDS to LVDS Connection
External 100ohm and AC blocking caps
Some input structures may not have an internal 100 ohm
resistor on the input and will need an external 100ohm
resistor for impedance matching. Also, the input may have
an internal DC bias which may not be compatible with
LVDS levels, AC blocking capacitors can be used.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
After installing the J-LINK driver, I opened Keil and started debugging. After the following prompt appeared, it closed automatically. What is the problem? [[i] This post was last edited by dongsy2012...
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stm32/stm8
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