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IDT74FCT16646ETE

Description
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56
Categorylogic    logic   
File Size177KB,9 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT74FCT16646ETE Overview

Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56

IDT74FCT16646ETE Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeDFP
package instructionDFP,
Contacts56
Reach Compliance Codecompliant
Other featuresWITH DIRECTION CONTROL
seriesFCT
JESD-30 codeR-GDFP-F56
JESD-609 codee0
length18.288 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
Number of digits8
Number of functions2
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
Peak Reflow Temperature (Celsius)225
propagation delay (tpd)3.8 ns
Certification statusNot Qualified
Maximum seat height2.1844 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width9.652 mm
Base Number Matches1
Integrated Device Technology, Inc.
FAST CMOS 16-BIT BUS
IDT54/74FCT16646T/AT/CT/ET
IDT54/74FCT162646T/AT/CT/ET
TRANSCEIVER/
REGISTERS (3-STATE)
74FCT162646T/AT/CT/ET 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power devices are organized as two inde-
pendent 8-bit bus transceivers with 3-state D-type registers.
The control circuitry is organized for multiplexed transmission
of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register fea-
tures direction control (xDIR), over-riding Output Enable con-
trol (x
OE
) and Select lines (xSAB and xSBA) to select either
real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data
bus, or both, can be stored in the internal registers by the
LOW-to-HIGH transitions at the appropriate clock pins. Flow-
through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The IDT54/74FCT16646T/AT/CT/ET are ideally suited for
driving high-capacitance loads and low-impedance
backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used
as backplane drivers.
The IDT54/74FCT162646T/AT/CT/ET have balanced
output drive with current limiting resistors. This offers low
ground bounce, minimal undershoot, and controlled output
fall times–reducing the need for external series terminating
resistors. The IDT54/74FCT162646T/AT/CT/ET are plug-in
replacements for the IDT54/74FCT16646T/AT/CT/ET and
54/74ABT16646 for on-board bus interface applications.
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
Typical t
SK
(o) (Output Skew) < 250ps
– Low input and output leakage
≤1µA
(max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– V
CC
= 5V
±10%
• Features for FCT16646T/AT/CT/ET:
– High drive outputs (-32mA I
OH
, 64mA I
OL
)
– Power off disable outputs permit “live insertion”
– Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25°C
• Features for FCT162646T/AT/CT/ET:
– Balanced Output Drivers:
±24mA
(commercial),
±16mA
(military)
– Reduced system switching noise
– Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25°C
DESCRIPTION:
The IDT54/74FCT16646T/AT/CT/ET and IDT54/
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
DIR
1
CLKBA
1
SBA
1
CLKAB
1
SAB
B REG
2
OE
2
DIR
2
CLKBA
2
SBA
2
CLKAB
2
SAB
B REG
D
C
1
A
1
A REG
1
B
1
2
A
1
A REG
D
C
2
B
1
D
C
D
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2540 drw 01
2540 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-4231/9
5.13
1

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