5.4 Soft Start Delay and Ramp Times ........................................................................................................................................ 15
5.5 Power Good ......................................................................................................................................................................... 16
5.6 Switching Frequency and PLL ............................................................................................................................................. 17
5.7 Power Train Component Selection ...................................................................................................................................... 18
5.8 Current Limit Threshold Selection....................................................................................................................................... 22
5.14 Adaptive Frequency Control .............................................................................................................................................. 27
6. Power Management Functional Description ................................................................................................................................. 28
6.6 Voltage Tracking ................................................................................................................................................................. 30
6.7 Voltage Margining ............................................................................................................................................................... 31
6.8 External Voltage Monitoring ............................................................................................................................................... 31
6.11 Digital-DC Bus .................................................................................................................................................................. 33
6.15 Active Current Sharing ...................................................................................................................................................... 35
6.18 Temperature Monitoring Using the XTEMP Pin ............................................................................................................... 37
6.20 Non-Volatile Memory and Device Security Features ........................................................................................................ 38
8. Ordering Information .................................................................................................................................................................... 40
9. Related Tools and Documentation ................................................................................................................................................ 40
10. Revision History ......................................................................................................................................................................... 41
FN6846 Rev. 3.00
February 15, 2011
Page 2 of 42
ZL2004
1.
Electrical Characteristics
Table 1. Absolute Maximum Ratings
Operating beyond these limits may cause permanent damage to the device. Functional operation beyond the
Recommended Operating Conditions is not implied. Voltage measured with respect to SGND.
Parameter
Pin(s)
Value
Unit
DC supply voltage
Logic I/O voltage
VDD
CFG, DDC, EN, FC, ILIM, MGN, PG,
SA(0,1), SALRT, SCL, SDA, SS,
SYNC, VMON, V(0,1)
VSEN+, VSEN-, VTRK, XTEMP
ISENA, ISENB
VR
V25
DGND, SGND
–
–
All
-0.3 to 17
-0.3 to 6.5
V
V
Analog input voltages
MOSFET drive reference
Logic reference
Ground voltage differential
(V
DGND
-V
SGND
)
Junction temperature
Storage temperature range
Lead temperature
(soldering, 10 s)
-0.3 to 6.5
-1.5 to 6.5
-0.3 to 6.5
-0.3 to 3
-0.3 to +0.3
-55 to 150
-55 to 150
300
V
V
V
V
V
o
C
o
C
o
C
Table 2. Recommended Operating Conditions and Thermal Information
Symbol
Parameter
Input Supply Voltage Range
V
DD
Output Voltage Range (Inductor sensing)
1
Operating Junction Temperature Range
Junction to Ambient Thermal Impedance
2
Junction to Case Thermal Impedance
3
V
OUT
T
J
Θ
JA
Θ
JC
Min
4.5
0.54
-40
–
–
Typ
–
Max
14
4.0
Unit
V
V
°C
°C/W
°C/W
–
35
5
125
–
–
Notes:
1. Includes margin limits.
2. Θ
JA
is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance
ground plane using multiple vias.
3. For Θ
JC
, the “case” temperature is measured at the center of the exposed metal pad.
FN6846 Rev. 3.00
February 15, 2011
Page 3 of 42
ZL2004
Table 3.
Electrical Specifications
V
DD
= 12 V, T
A
= -40C to 85C unless otherwise noted. Typical values are at T
A
= 25C.
Boldface limits apply over
the operating temperature range, -40°C to +85°C.
Parameter
Input and Supply Characteristics
I
DD
supply current at f
SW
= 200 kHz
I
DD
supply current at f
SW
= 1.4 MHz
I
DDS
shutdown current
VR reference output voltage
V25 reference output voltage
Output Characteristics
Output voltage adjustment range
1
Output voltage set-point resolution
Output voltage accuracy
3
VSEN input bias current
Current sense differential input
voltage (V
OUT
referenced)
Current sense input bias current
(V
OUT
referenced, V
OUT
<= 3.6V)
Soft start delay duration range
Conditions
GH no load, GL no load,
MISC_CONFIG[7] = 1
EN = 0 V, No I
2
C/SMBus activity
V
DD
> 6 V, I
VR
< 50 mA
V
R
> 3 V, I
V25
< 50 mA
V
IN
> V
OUT
Set using resistors
Set using I
2
C/SMBus
Includes line, load, temp
VSEN = 4 V
V
ISENA
- V
ISENB
ISENA
ISENB
Set using SS pin or resistor
Set using I
2
C/SMBus
Turn-on delay (precise mode)
4,5
Turn-on delay (normal mode)
6
Turn-off delay
6
Set using SS pin or resistor
Set using I
2
C
Min
10
–
–
–
4.5
2.25
0.6
–
–
-1
–
- 50
-1
- 100
2
0.002
–
–
–
2
0
–
- 10
-1
–
–
2.0
–
2.25
Typ
16
25
6.5
5.2
2.5
–
10
±0.025
–
80
–
–
–
–
–
±0.25
-0.25/+4
-0.25/+4
–
–
100
–
–
–
1.4
–
–
–
Max
10
30
50
8
5.7
2.75
3.6
–
–
1
150
50
1
100
20
500
–
–
–
20
200
–
10
1
0.8
–
–
0.4
–
Unit
mA
mA
mA
V
V
V
mV
% FS
2
%
µA
mV
µA
µA
ms
s
ms
ms
ms
ms
ms
µs
µA
mA
V
V
V
V
V
Soft start delay duration accuracy
Soft start ramp duration range
Soft start ramp duration accuracy
Logic Input/Output Characteristics
Logic input bias current
MGN input bias current
Logic input low, V
IL
Logic input OPEN (N/C)
Logic input high, V
IH
Logic output low, V
OL
Logic output high, V
OH
Notes:
EN,PG,SCL,SDA,SALRT pins
Multi-mode logic pins
I
OL
≤ 4 mA
I
OH
≥ -2 mA
1. Set point adjustment range does not include margin limits.
2. Percentage of Full Scale (FS) with temperature compensation applied.
3. V
OUT
set-point measured at the termination of the VSEN+ and VSEN- sense points.
4. The device requires approximately 2 ms following an enable signal and prior to ramping its output. The delay accuracy will vary by
±0.25 ms around the 2 ms minimum delay value.
5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
6. The devices may require up to a 4 ms delay following an assertion of the enable signal (normal mode) or following the de-assertion
of the enable signal.
FN6846 Rev. 3.00
February 15, 2011
Page 4 of 42
ZL2004
Table 3. Electrical Characteristics (continued)
V
DD
= 12 V, T
A
= -40C to 85C unless otherwise noted. Typical values are at T
A
= 25C.
Parameter
Oscillator and Switching Characteristics
Switching frequency range
Switching frequency set-point accuracy
Maximum PWM duty cycle
Minimum SYNC pulse width
Input clock frequency drift tolerance
Tracking
VTRK input bias current
VTRK tracking ramp accuracy
VTRK regulation accuracy
Fault Protection Characteristics
UVLO threshold range
UVLO set-point accuracy
UVLO hysteresis
UVLO delay
Power good V
OUT
low threshold
Power good V
OUT
high threshold
Power good V
OUT
hysteresis
Power good delay
VSEN undervoltage threshold
VSEN overvoltage threshold
VSEN undervoltage hysteresis
VSEN undervoltage/ overvoltage fault
response time
Current limit set-point accuracy
(V
OUT
referenced)
Current limit protection delay
Temperature compensation of
current limit protection threshold
Thermal protection threshold (junction
temperature)
Thermal protection hysteresis
Notes:
Conditions
Min
10
200
-5
95
150
- 13
–
- 100
-1
2.85
- 150
–
0
–
–
–
–
2
0
–
0
–
0
–
–
5
–
Typ
–
–
–
–
–
110
–
–
–
–
3
–
–
90
115
5
–
–
85
–
115
–
5
16
–
±10
5
–
4400
125
–
15
Max
10
1400
5
–
–
13
200
+ 100
1
16
150
–
100
2.5
–
–
–
20
500
–
110
–
115
–
–
60
–
–
32
12700
–
125
–
Unit
kHz
%
%
ns
%
µA
mV
%
V
mV
%
%
µs
% V
OUT
% V
OUT
%
ms
s
% V
OUT
% V
OUT
% V
OUT
% V
OUT
% V
OUT
µs
µs
% FS
8
t
SW 9
t
SW 9
ppm /
°C
°C
°C
°C
Factory default
External clock source
VTRK = 4.0 V
100% Tracking, V
OUT
- VTRK
100% Tracking, V
OUT
- VTRK
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Factory default
Factory default
Using pin-strap or resistor
7
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
–
1
100
–
- 40
–
7. Factory default Power Good delay is set to the same value as the soft start ramp time.
8. Percentage of Full Scale (FS) with temperature compensation applied.
9. t
SW
= 1/f
SW
, where f
SW
is the switching frequency.
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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