Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
Model
AD7888AR
AD7888BR
AD7888ARU
AD7888BRU
EVAL-AD7888CB
2
EVAL-CONTROL BRD2
3
NOTES
1
Linearity error here refers to integral linearity error.
2
This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.
3
This board is a complete unit allowing a PC to control and communicate with all
Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7888 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD7888
TIMING SPECIFICATIONS
1
(T = T
A
MIN
to T
MAX
, unless otherwise noted)
Parameter
f
SCLK2
t
CONVERT
t
ACQ
t
1
t
2 3
t
3 3
t
4
t
5
t
6
t
7
t
8 4
t
9
Limit at T
MIN
, T
MAX
(A, B Versions)
4.75 V to 5.25 V
2.7 V to 3.6 V
2
14.5 t
SCLK
1.5 t
SCLK
10
30
75
20
20
0.4 t
SCLK
0.4 t
SCLK
80
5
2
14.5 t
SCLK
1.5 t
SCLK
10
60
100
20
20
0.4 t
SCLK
0.4 t
SCLK
80
5
Unit
MHz max
Description
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs
typ
Throughput Time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
CS
to SCLK Setup Time
Delay from
CS
until DOUT 3-State Disabled
Data Access Time after SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to DOUT High Impedance
Power-Up Time from Shutdown
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V
±
10% and time for an output to
cross 0.4 V or 2.0 V with V
DD
= 3 V
±
10%.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200 A
I
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
200 A
I
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
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Embedded System
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