EEWORLDEEWORLDEEWORLD

Part Number

Search

SFML-147-L1-LM-D-TR

Description
Board Connector, 94 Contact(s), 2 Row(s), Female, Straight, Solder Terminal, Socket,
CategoryThe connector    The connector   
File Size2MB,4 Pages
ManufacturerSAMTEC
Websitehttp://www.samtec.com/
Environmental Compliance  
Download Datasheet Parametric View All

SFML-147-L1-LM-D-TR Overview

Board Connector, 94 Contact(s), 2 Row(s), Female, Straight, Solder Terminal, Socket,

SFML-147-L1-LM-D-TR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSAMTEC
Reach Compliance Codecompliant
ECCN codeEAR99
Body/casing typeSOCKET
Connector typeBOARD CONNECTOR
Contact to complete cooperationGOLD
Contact completed and terminatedMATTE TIN
Contact point genderFEMALE
Contact materialPHOSPHOR BRONZE/BERYLLIUM COPPER
DIN complianceNO
Filter functionNO
IEC complianceNO
JESD-609 codee3
MIL complianceNO
Manufacturer's serial numberSFML
Mixed contactsNO
Installation methodSTRAIGHT
Installation typeBOARD
Number of rows loaded2
OptionsGENERAL PURPOSE
Terminal pitch1.27 mm
Termination typeSOLDER
Total number of contacts94
Base Number Matches1
TABLE 1
STYLE
-X1
-X3
"A"
"B"
.120 [3.05] .020 [.51]
.075 [1.91] .016 [.41]
S A M TE C
*
5 2 0 P A R K E A S T B L V D , N E W A L B A N Y , IN 4 7 1 5 0
P H O N E : 8 1 2 .9 4 4 .6 7 3 3
F A X : 8 1 2 .9 4 8 .5 0 4 7
e -M ail:
IN F O @ S A M T E C .C O M
C O D E: 55322
How to design a delay device using VHDL
The input is some randomly generated signals, and all these input signals are required to be output sequentially after a delay of 100 clock cycles. How should this be designed ? Thank you!...
eeleader-mcu FPGA/CPLD
Embedded
I heard that embedded systems are very popular recently... But I still don't know what embedded systems are for? It seems that there are ARM and Linux directions, etc. If I want to get involved in thi...
lindandaixu ARM Technology
MOJO V3 ISE Engineering
ISE newly built MOJO V3 projectStep 1: Launch ISEStep 2: Create a new projectStep 3: Create a new fileStep 4: SynthesisStep 5: Set the pins and save them casually, and then modify the UCF fileAfter ed...
xutong FPGA/CPLD
Beaglebone peripheral circuit design driver code modification
Modified according to TI Android ICS 4.0.3 DevKitV3.0.1 AM335x EMV-SK Sources. [b]1 Modify to support the user indicator light on beaglebone:[/b] Modified source code location: [color=#000][font=Helve...
523335234 DSP and ARM Processors
Let's take a look at the operation panel of the old inverter
As shown in the figure below, the main control chip in this operation board is STC89LE52, and the communication with the device is in the form of a serial port. In order to ensure the reliability of c...
wugx 51mcu
Tips for Improving Timing and FPGA Resource Utilization
1. If a signal is generated by multiple signals through complex combinational logic and timing logic, then the combinational logic should be evenly distributed in front of each reg variable. It should...
eeleader FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1662  2606  1270  1129  910  34  53  26  23  19 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号