L-TTSI004161BL-2 datasheet, PDF

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L-TTSI004161BL-2: DescriptionTime Slot Assigner, PBGA240, ROHS COMPLIANT, PLASTIC, BGA-240; CategoryWireless rf/communication Telecom circuit; File Size1001KB，61 Pages; ManufacturerLSC/CSI; Websitehttps://lsicsi.com; Environmental Compliance

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L-TTSI004161BL-2 Overview

Time Slot Assigner, PBGA240, ROHS COMPLIANT, PLASTIC, BGA-240

L-TTSI004161BL-2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	LSC/CSI
Parts packaging code	BGA
package instruction	BGA,
Contacts	240
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B240
JESD-609 code	e1
length	19 mm
Number of functions	1
Number of terminals	240
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	2.07 mm
Nominal supply voltage	1.5 V
surface mount	YES
Telecom integrated circuit types	TIME SLOT ASSIGNER
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	19 mm
Base Number Matches	1

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Data Sheet

May 27, 2005

TSI-4

4k x 4k Time-Slot Interchanger

1 Introduction

This document consists of two major sections:

The TTSI004161 device hardware description. This section contains ball information, operating conditions, dc electrical

characteristics, timing diagrams, ac characteristics, and packaging information.

The TTSI004161 device register description. This section contains register information.

1.1 Related Documents

The documentation package for this device consists of the following documents:

The

TSI-4 4k x 4k Time-Slot Interchanger

Product Brief, the

TSI Family Selection Guide,

the

TSI-4 4k x 4k Time-Slot

Interchanger

Data Sheet, (this document), and the

TTSI-144 Scalable Time-Slot Interchanger System Design Guide.

These documents are available on the public website shown below.

If the reader displays this document using

Acrobat Reader

, clicking on any blue text will bring the reader to that reference

point.

To access related documents, including the documents mentioned above, please go to the following public website, or con-

tact your Agere representative (see the last page of this document).

http://www.agere.com/telecom/time_slot_interchangers.html

1.2 Block Diagram and High-Level Interface Definition

TEST PATTERN

MONITOR

TEST ACCESS

PORT

TEST PATTERN

GENERATOR

SWITCH

FABRIC

RECEIVE

CHI

TRANSMIT

CHI

DATA

STORE

WRITE ADDRESS

COUNTER

CONNECTION

STORE

READ ADDRESS

COUNTER

MICROPROCESSOR

INTERFACE

CLOCK

GENERATOR

Figure 1-1. Block Diagram and High-Level Interface Definition

TSI-4

4k x 4k Time-Slot Interchanger

Data Sheet

May 27, 2005

Table of Contents

Contents

Page

1 Introduction .........................................................................................................................................................................1

1.1 Related Documents .....................................................................................................................................................1

1.2 Block Diagram and High-Level Interface Definition .....................................................................................................1

2 Ball Information ...................................................................................................................................................................7

2.1 Top View Ball Diagram ................................................................................................................................................7

2.2 Package Ball Assignments ..........................................................................................................................................8

2.3 Package Ball Matrix ...................................................................................................................................................10

2.3.1 Top View ..........................................................................................................................................................10

2.3.2 Bottom View .....................................................................................................................................................11

2.4 Ball Types ..................................................................................................................................................................12

2.5 Ball Definitions ...........................................................................................................................................................12

3 Operating Conditions and Reliability ................................................................................................................................15

3.1 Absolute Maximum Ratings .......................................................................................................................................15

3.2 Recommended Operating Conditions .......................................................................................................................15

3.3 Handling Precautions ................................................................................................................................................15

3.4 Thermal Parameters (Definitions and Values) ...........................................................................................................16

3.5 Power Consumption ..................................................................................................................................................17

4 dc Electrical Characteristics .............................................................................................................................................18

5 Timing Diagrams and ac Characteristics ..........................................................................................................................19

6 Register Description .........................................................................................................................................................31

6.1 Device Addressing Notes ..........................................................................................................................................31

6.2 Acronyms Used .........................................................................................................................................................31

6.3 Address Map .............................................................................................................................................................31

6.4 Register Summary .....................................................................................................................................................32

6.5 Global Control Registers ...........................................................................................................................................34

6.6 Connection Store Generator Registers .....................................................................................................................39

6.7 Test Pattern Generator and Monitor Registers ..........................................................................................................44

6.8 Concentration Highway Configuration Registers .......................................................................................................48

7 Switch Fabric Control .......................................................................................................................................................54

8 Connection Store ..............................................................................................................................................................58

9 Outline Diagrams ..............................................................................................................................................................60

10 Ordering Information .......................................................................................................................................................61

Agere Systems Inc.

Data Sheet

May 27, 2005

TSI-4

4k x 4k Time-Slot Interchanger

Table of Contents

(continued)

Contents

Page

Table 2-1. Package Ball Assignments in Signal Name Order.................................................................................................8

Table 2-2. Package Ball Assignments (Top View) ................................................................................................................10

Table 2-3. Package Ball Assignments (Bottom View)........................................................................................................... 11

Table 2-4. Ball Types ............................................................................................................................................................12

Table 2-5. Timing Port ..........................................................................................................................................................12

Table 2-6. Transmit and Receive Concentration Highways ..................................................................................................12

Table 2-7. Control Port..........................................................................................................................................................13

Table 2-8. Initialization and Test Access...............................................................................................................................13

Table 2-9. Power Balls..........................................................................................................................................................14

Table 3-1. Absolute Maximum Ratings .................................................................................................................................15

Table 3-2. Operating Conditions ...........................................................................................................................................15

Table 3-3. ESD Tolerance.....................................................................................................................................................15

Table 3-4. Thermal Parameter Values ..................................................................................................................................16

Table 3-5. Power Consumption ............................................................................................................................................17

Table 4-1. CMOS Inputs .......................................................................................................................................................18

Table 4-2. CMOS Outputs ....................................................................................................................................................18

Table 4-3. CMOS Bidirectionals (DATA[15:0]) ......................................................................................................................18

Table 5-1. CHICLK Timing Specifications .............................................................................................................................19

Table 5-2. MPUCLK Timing Specifications ...........................................................................................................................19

Table 5-3. ac Timing Measurement Specification .................................................................................................................20

Table 5-4. CHI Interface Timing ............................................................................................................................................21

Table 5-5. CHI 3-State Output Control..................................................................................................................................27

Table 5-6. Microprocessor Port Timing—Read Cycle...........................................................................................................28

Table 5-7. Microprocessor Port Timing—Write Cycle ...........................................................................................................29

Table 6-1. Address Map........................................................................................................................................................31

Table 6-2. Global Registers ..................................................................................................................................................32

Table 6-3. Connection Store Generator Registers................................................................................................................32

Table 6-4. Test Pattern Generator and Monitor Registers ....................................................................................................33

Table 6-5. Concentration Highway Configuration Registers .................................................................................................33

Table 6-6. Switch Fabric Control...........................................................................................................................................33

Table 6-7. Connection Store .................................................................................................................................................34

Table 6-8. Reserved Registers .............................................................................................................................................34

Table 6-9. Version_Control (Read Only)...............................................................................................................................34

Table 6-10. Chip_Identity (Read Only) .................................................................................................................................34

Table 6-11. Summary_Interrupt_Status (Read Only) ............................................................................................................35

Table 6-12. Summary_Interrupt_Mask (Read/Write) ............................................................................................................35

Table 6-13. CPU_Access_Error (CORWN) ..........................................................................................................................36

Table 6-14. CPU_Access_Error_Mask (Read/Write)............................................................................................................36

Table 6-15. Global_Control (Read/Write) .............................................................................................................................37

Table 6-16. PLL_Control (Read/Write) .................................................................................................................................38

Table 6-17. Power_Control (Read/Write)..............................................................................................................................38

Table 6-18. Invalid_Address_Trap (Read Only)....................................................................................................................38

Table 6-19. Scratch_Register (Read/Write)..........................................................................................................................38

Table 6-20. Reserved_0 (Read/Write) ..................................................................................................................................39

Table 6-21. CSG_Control (Read/Write) ................................................................................................................................39

Table 6-22. CSG_Status (Read Only)...................................................................................................................................40

Table 6-23. CSG_Starting_Address (Read/Write) ................................................................................................................40

Table 6-24. CSG_Ending_Address (Read/Write) .................................................................................................................40

Table 6-25. CSG_Write_Enable_Low (Read/Write)..............................................................................................................40

Table 6-26. CSG_Write_Enable_High (Read/Write).............................................................................................................40

Table 6-27. CSG_Seed_Low (Read/Write)...........................................................................................................................41

Table 6-28. CSG_Seed_High (Read/Write)..........................................................................................................................41

Agere Systems Inc.

TSI-4

4k x 4k Time-Slot Interchanger

Data Sheet

May 27, 2005

Table of Contents

(continued)

Tables

Page

Table 6-29. CSG_OR_Mask_Low (Read/Write) ...................................................................................................................41

Table 6-30. CSG_OR_Mask_High (Read/Write) ..................................................................................................................41

Table 6-31. CSG_AND_Mask_Low (Read/Write) .................................................................................................................42

Table 6-32. CSG_AND_Mask_High (Read/Write) ................................................................................................................42

Table 6-33. CS_Stream_Control (Read/Write) .....................................................................................................................42

Table 6-34. CSG_Configuration (Read/Write) ......................................................................................................................43

Table 6-35. TPG_Configuration (Read/Write).......................................................................................................................44

Table 6-36. TPG_User_Pattern (Read/Write) .......................................................................................................................44

Table 6-37. TPM_Configuration (Read/Write) ......................................................................................................................45

Table 6-38. TPM_User_Pattern (Read/Write).......................................................................................................................45

Table 6-39. TPM_Error_Count (Sat/Roll*) ............................................................................................................................46

Table 6-40. TPG_Inject_Error_Count (Write Only) ...............................................................................................................46

Table 6-41. TPG_Data_Invert_Mask (Read/Write) ...............................................................................................................46

Table 6-42. TPM_Status (Read Only)...................................................................................................................................47

Table 6-43. TPM_Status_Mask (Read/Write) .......................................................................................................................47

Table 6-44. Receive_CHI_Configuration (Read/Write) .........................................................................................................48

Table 6-45. Receive_CHI_Status (CORWN) Receive_CHI_Status (CORWN).....................................................................48

Table 6-46. Receive_CHI_Status_Mask (Read/Write)..........................................................................................................49

Table 6-47. Receive_CHI_Global_Configuration (Read/Write) ............................................................................................49

Table 6-48. Transmit_CHI_Configuration (Read/Write) ........................................................................................................50

Table 6-49. Transmit_CHI_Status (CORWN) .......................................................................................................................51

Table 6-50. Transmit_CHI_Status_Mask (Read/Write).........................................................................................................51

Table 6-51. Transmit_CHI_Global_Configuration (Read/Write)............................................................................................52

Table 6-52. Receive_CHI_Time_Slot_Offset (Read/Write)...................................................................................................53

Table 6-53. Transmit_CHI_Time_Slot_Offset (Read/Write)..................................................................................................53

Table 7-1. SF_Status (CORWN) ...........................................................................................................................................54

Table 7-2. SF_Status_Mask (Read/Write) ............................................................................................................................54

Table 7-3. Data_Store_Time_Slot_Capture_Select (Read/Write).........................................................................................55

Table 7-4. Data_Store_Captured_Data (Read Only) ............................................................................................................55

Table 7-5. Connection_Store_Parity_Error_Address_Trap (CORWN) .................................................................................56

Table 7-6. Receive_Link_Offset (Read Only) .......................................................................................................................56

Table 7-7. Transmit_Link_Offset (Read/Write) .....................................................................................................................56

Table 7-8. Wide_Mode_Control (Read/Write).......................................................................................................................57

Table 8-1. Low_Control_Word (Read/Write).........................................................................................................................58

Table 8-2. High_Control_Word (Read/Write) ........................................................................................................................59

Agere Systems Inc.

Data Sheet

May 27, 2005

TSI-4

4k x 4k Time-Slot Interchanger

Table of Contents

(continued)

Figures

Page

Figure 1-1. Block Diagram and High-Level Interface Definition..............................................................................................1

Figure 2-1. Package Diagram (Top View) ..............................................................................................................................7

Figure 5-1. CHICLK Timing Specifications ...........................................................................................................................19

Figure 5-2. MPUCLK Timing Specifications .........................................................................................................................19

Figure 5-3. ac Timing Measurement Specification ...............................................................................................................20

Figure 5-4. CHI Interface Timing ..........................................................................................................................................21

Figure 5-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK.............................................22

Figure 5-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK ........................................................22

Figure 5-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK...............................................23

Figure 5-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK ..........................................................23

Figure 5-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK...............................................24

Figure 5-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK ........................................................24

Figure 5-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK.............................................25

Figure 5-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK ........................................................25

Figure 5-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK...............................................26

Figure 5-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK ..........................................................26

Figure 5-15. CHI 3-State Output Control ..............................................................................................................................27

Figure 5-16. Microprocessor Port Timing—Read Cycle .......................................................................................................28

Figure 5-17. Microprocessor Port Timing—Write Cycle .......................................................................................................29

Figure 6-1. Transmit CHI Configuration (R/W) .....................................................................................................................50

Agere Systems Inc.

L-TTSI004161BL-2 Related Products

	L-TTSI004161BL-2	TTSI004161BL-2
Description	Time Slot Assigner, PBGA240, ROHS COMPLIANT, PLASTIC, BGA-240	Time Slot Assigner, PBGA240, PLASTIC, BGA-240
Is it lead-free?	Lead free	Contains lead
Is it Rohs certified?	conform to	incompatible
Maker	LSC/CSI	LSC/CSI
Parts packaging code	BGA	BGA
package instruction	BGA,	BGA,
Contacts	240	240
Reach Compliance Code	compliant	compliant
JESD-30 code	S-PBGA-B240	S-PBGA-B240
JESD-609 code	e1	e0
length	19 mm	19 mm
Number of functions	1	1
Number of terminals	240	240
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	225
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.07 mm	2.07 mm
Nominal supply voltage	1.5 V	1.5 V
surface mount	YES	YES
Telecom integrated circuit types	TIME SLOT ASSIGNER	TIME SLOT ASSIGNER
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN SILVER COPPER	TIN LEAD
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	30
width	19 mm	19 mm
Base Number Matches	1	1

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