LC4128B-3T128C datasheet, PDF - EEWORLD Datasheet

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LC4128B-3T128C: DescriptionEE PLD, 4ns, 128-Cell, CMOS, PQFP128, TQFP-128; CategoryProgrammable logic devices Programmable logic; File Size697KB，67 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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LC4128B-3T128C Overview

EE PLD, 4ns, 128-Cell, CMOS, PQFP128, TQFP-128

LC4128B-3T128C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Lattice
Parts packaging code	QFP
package instruction	TQFP-128
Contacts	128
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	YES
maximum clock frequency	200 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G128
JESD-609 code	e0
JTAG BST	YES
length	14 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	92
Number of macro cells	128
Number of terminals	128
organize	0 DEDICATED INPUTS, 92 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP128,.64SQ,16
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	1.8/3.3,2.5 V
Programmable logic type	EE PLD
propagation delay	4 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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ispMACH 4000V/B/C Family

3.3V/2.5V/1.8V In-System Programmable

SuperFAST

High Density PLDs

May 2002

Data Sheet

Features

■

High Performance

• f

MAX

= 380MHz maximum operating frequency

• t

= 2.5ns propagation delay

• Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

■

Broad Device Offering

•

32 to 512 macrocells

30 to 208 I/O pins

44 to 256 pins/balls in TQFP or fpBGA packages

Commercial and industrial temperature ranges

■

Easy System Integration

■

Ease of Design

• Enhanced macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-Fit

and reﬁt

• Fast path, SpeedLocking

Path, and wide-PT

path

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

• 1.8V core E

CMOS

technology

• CMOS design techniques provide low static and

dynamic power

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• Operation with 3.3V (4000V), 2.5V (4000B) or

1.8V (4000C) supplies

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Programmable output slew rate

• 3.3V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V In-System Programmable

(ISP™) using IEEE 1532 compliant interface

• I/O pins with fast setup path

■

Low Power

Table 1. ispMACH 4000V/B/C Family Selection Guide

ispMACH

4032V/B/C*

Macrocells

User I/O Options

(ns)

MAX

(MHz)

Supply Voltages (V)

Pins/Package

30/32

2.5

1.8

2.2

380

3.3/2.5/1.8V

44 TQFP

48 TQFP

ispMACH

4064V/B/C*

30/32/64

2.5

1.8

2.2

380

3.3/2.5/1.8V

44 TQFP

48 TQFP

100 TQFP

ispMACH

4128V/B/C*

128

64/92

3.0

2.2

2.8

300

3.3/2.5/1.8V

ispMACH

4256V/B/C*

256

64/128/160

3.0

2.2

2.8

300

3.3/2.5/1.8V

ispMACH

4384V/B/C*

384

128/192

3.5

2.2

3.0

300

3.3/2.5/1.8V

ispMACH

4512V/B/C*

512

128/208

3.5

2.2

3.0

300

3.3/2.5/1.8V

100 TQFP

128 TQFP

100 TQFP

176 TQFP

256 fpBGA**

176 TQFP

256 fpBGA

176 TQFP

256 fpBGA

*Preliminary

**128-I/O and 160-I/O conﬁgurations.

www.latticesemi.com

ispm4k_07

Lattice Semiconductor

ispMACH 4000V/B/C Family Data Sheet

The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can

support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-

patible with the power supply provided to the bank. Support for a variety of standards helps designers implement

designs in mixed voltage environments.

ispMACH 4000 Architecture

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has

36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be

connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still

must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and

predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-

ated I/O cells in the I/O block.

Generic Logic Block

The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock

generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-

pled from macrocells through the ORP. Figure 2 illustrates the GLB.

Figure 2. Generic Logic Block

CLK0

CLK1

CLK2

CLK3

To GRP

Clock

Generator

1+OE

16 MC Feedback Signals

1+OE

To ORP

Product Term

Output Enable

Sharing

Logic Allocator

36 Inputs

from GRP

AND Array

The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are

used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-

nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic

allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and

Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being

fed to the macrocells.

Every set of

ﬁve

product terms from the 80 logic product terms forms a product term cluster starting with PT0.

There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND

Array.

AND Array

36 Inputs,

83 Product Terms

16 Macrocells

LC4128B-3T128C Related Products

	LC4128B-3T128C	LC4128C-3T100C	LC4128C-3T128C	LC4128V-3T100C	LC4128V-3T128C	LC4128B-3T100C
Description	EE PLD, 4ns, 128-Cell, CMOS, PQFP128, TQFP-128	EE PLD, 4ns, 128-Cell, CMOS, PQFP100, TQFP-100	EE PLD, 4ns, 128-Cell, CMOS, PQFP128, TQFP-128	EE PLD, 4ns, 128-Cell, CMOS, PQFP100, TQFP-100	EE PLD, 4ns, 128-Cell, CMOS, PQFP128, TQFP-128	EE PLD, 4ns, 128-Cell, CMOS, PQFP100, TQFP-100
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	TQFP-128	TQFP-100	TQFP-128	TQFP-100	TQFP-128	TQFP-100
Contacts	128	100	128	100	128	100
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	YES	2.5V AND 3.3V SUPPLY VOLTAGE ALSO AVAILABLE	2.5V AND 3.3V SUPPLY VOLTAGE ALSO AVAILABLE	YES	YES	YES
maximum clock frequency	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz
In-system programmable	YES	YES	YES	YES	YES	YES
JESD-30 code	S-PQFP-G128	S-PQFP-G100	S-PQFP-G128	S-PQFP-G100	S-PQFP-G128	S-PQFP-G100
JESD-609 code	e0	e0	e0	e0	e0	e0
JTAG BST	YES	YES	YES	YES	YES	YES
length	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Humidity sensitivity level	3	3	3	3	3	3
Number of I/O lines	92	64	92	64	92	64
Number of macro cells	128	128	128	128	128	128
Number of terminals	128	100	128	100	128	100
organize	0 DEDICATED INPUTS, 92 I/O	0 DEDICATED INPUTS, 64 I/O	0 DEDICATED INPUTS, 92 I/O	0 DEDICATED INPUTS, 64 I/O	0 DEDICATED INPUTS, 92 I/O	0 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
Encapsulate equivalent code	QFP128,.64SQ,16	QFP100,.63SQ,20	QFP128,.64SQ,16	QFP100,.63SQ,20	QFP128,.64SQ,16	QFP100,.63SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240	240	240	240	240	240
power supply	1.8/3.3,2.5 V	1.8,1.8/3.3 V	1.8,1.8/3.3 V	1.8/3.3,3.3 V	1.8/3.3,3.3 V	1.8/3.3,2.5 V
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	4 ns	4 ns	4 ns	4 ns	4 ns	4 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage	2.7 V	1.95 V	1.95 V	3.6 V	3.6 V	2.7 V
Minimum supply voltage	2.3 V	1.65 V	1.65 V	3 V	3 V	2.3 V
Nominal supply voltage	2.5 V	1.8 V	1.8 V	3.3 V	3.3 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.4 mm	0.5 mm	0.4 mm	0.5 mm	0.4 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30	30
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	1	1	1
Is Samacsys	-	N	N	N	N	-

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