Si5321
SONET/SDH P
R E C I S IO N
C
LOCK
M
ULTIPLIER
I C
Features
Ultra-low jitter clock output with jitter
generation as low as 0.3 ps
RMS
No external components (other than a
resistor and bypassing)
Input clock ranges at 19, 39, 78, 155,
311, or 622 MHz
Output clock ranges at 19, 39, 78, 155,
311, 622, 1244, or 2488 MHz
Maximum range includes 693 MHz for
10 GbE FEC support
Digital hold for loss-of-input clock
Support for 255/238 (15/14),
255/237 (85/79), and 66/64 FEC scaling
(ITU-T G.709 and IEEE 802.3ae)
Selectable loop bandwidth
Loss-of-signal alarm output
Low power
Small size (9 x 9 mm)
Backwards compatible with Si5320
Si5321
Si5321
Applications
Ordering Information:
See page 30.
SONET/SDH line/port cards
Terabit routers
Core switches
Digital cross connects
Description
The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed
communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device
phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range
and generates a frequency-multiplied clock output that can be configured for operation
in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories
DSPLL
®
technology provides PLL functionality with unparalleled performance. It
eliminates external loop filter components, provides programmable loop parameters,
and simplifies design. FEC rates are supported by selectable forward and reverse 255/
238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. The ITU-T G.709
255/237 rate and the IEEE 802.3ae 66/64 rate are supported when using a 155 MHz or
higher rate input clock. The performance and integration of Silicon Laboratories’ Si5321
clock IC provides high-level support of the latest specifications and systems. It operates
from a single 3.3 V supply.
Functional Block Diagram
REXT
VSEL33
VDD
GND
Biasing & Supply Regulation
FXDDELAY
CLKIN+
CLKIN–
2
CAL_ACTV
÷
Signal
Detect
3
2
DSPLL
®
DH_ACTV
÷
2
2
Calibration
CLKOUT+
CLKOUT–
FRQSEL[2:0]
RSTN/CAL
VALTIME
LOS
BWBOOST
BWSEL[1:0]
INFRQSEL[2:0] FEC[2:0]
Rev. 2.5 8/08
Copyright © 2008 by Silicon Laboratories
Si5321
Si5321
T
ABLE O F
C
ONTENTS
S
ECTION
P
AGE
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1. DSPLL
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.5. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3. Pin Descriptions: Si5321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. 9x9 mm PBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 2.5
3
Si5321
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5321 Supply Voltage
3
, 3.3 V Supply
Symbol
T
A
V
DD33
Test Condition
Min
1
–20
2
3.135
Typ
25
3.3
Max
1
85
3.465
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5321 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient
temperature of –20 to 85° C.
3.
The Si5321 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of Figure 5 on page 16.
4
Rev. 2.5
Si5321
C LKIN +
C LKIN –
V
IS
A. O peration with Single-Ended C lock Input*
N ote: W hen using single-ended clock sources, the unused clock
input on the Si5321 m ust be ac-coupled to ground.
C LKIN +
C LKIN –
0.5 V
ID
(C LKIN+) – (C LKIN –)
V
ID
B. O peration with D ifferential C lock Input
N ote: Transm ission line term ination, when required, m ust be provided
externally.
Figure 1. CLKIN Voltage Characteristics
80%
20%
t
F
t
R
Figure 2. Rise/Fall Time Measurement
(C L K IN + ) - (C L K IN - )
0 V
t
L O S
Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition
Rev. 2.5
5
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