Standard Products
UT54ACS164646S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver
Preliminary Datasheet
January 18, 2007
www.aeroflex.com/radhard
FEATURES
Flexible voltage operation
- 5V bus to 3.3V bus
- 3.3V bus to 5V bus
- 5V bus to 5V bus
- 3.3V bus to 3.3V bus
Independent registers for A and B buses
Multiplexed real-time and stored data
Flow-through architecture optimizes PCB layout
Cold- and Warm-sparing
- 750kΩ minimum input impedance power-off
- Guranteed output tri-state while one power supply is "off"
and the other is "on"
Schmitt trigger inputs to filter noisy signals
All inputs are 5V tolerant regardless of power supply voltage
0.6μm
Commercial RadHard CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
TM
DESCRIPTION
The UT54ACS164646S is a 16-bit, MultiPurpose, registered,
level shifting, bus transceiver consisting of D-type flip-flops,
control circuitry, and 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or from the
internal storage registers. The high-speed, low power
UT54ACS164646S transceiver is designed to perform multi-
ple functions including: asynchronous two-way communica-
tion, signal buffering, voltage translation, cold- and warm-
sparing. The device can be used as two independant 8-bit
transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the rising edge of the appropri-
ate clock (xCLKAB or xCLKBA) input. With either V
DD
sup-
ply equal to zero volts, the UT54ACS164646S outputs and
inputs present a minimum impedance of 750kΩ making it
ideal for “cold-spare” and "warm-spare" applications. By vir-
tue of its flexible power supply interface, the
UT54ACS164646S may operate as a 3.3-volt only, 5-volt only,
or mixed 3.3V/5V bus transceiver.
The Output-enable (xOE) and direction-control (xDIR) inputs
are provided to control the tri-state function and input/output
direction of the transceiver respectively. The select controls
(xSAB and xSBA) select whether stored register data or real-
time data is driven to the outputs as determined by the xDIR
inputs. The circuitry used for select control eliminates the typ-
ical decoding glitch that occurs in a multiplexer during the
transition between stored and real-time data. Regardless of the
selected operating mode ("real-time" or "recall"), a rising edge
on the port input clocks (xCLKAB and xCLKBA) will latch
the corresponding I/O states into their respective registers.
Furthermore, when a data port is isolated (xOE = high), A-port
data may be stored into its corresponding register while B-port
data may be independantly stored into its corresponding regis-
ters. Therefore, when an output function is disabled, the input
function is still enabled and may be used to store and transmit
data. Lastly, only one of the two buses, xA-port or xB-port,
may be driven at a time.
- SEU Onset LET >74 MeV-cm
2
/mg
High speed, low power consumption
Available QML Q or V processes
Standard Microcircuit Drawing: 5962-06234
Package:
- 56-pin ceramic flatpack
PIN DESCRIPTION
Pin Names
xOE
xDIR
xAx
xBx
xSAB
xSBA
xCLKAB
xCLKBA
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs (3.3V Port)
Side B Inputs or 3-State Outputs (5V Port)
Select real-time or stored A bus data to B bus
Select real-time or stored B bus data to A bus
Store A bus data
Store B bus data
1
POWER TABLE
Port B
5 Volts
5 Volts
3.3 Volts
V
SS
V
SS
3.3V or 5V
Port A
3.3 Volts
5 Volts
3.3 Volts
V
SS
3.3V or 5V
V
SS
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port A Warm Spare
Port B Warm Spare
I/O GUIDELINES
Control signals xDIR, xOE, xSAB, xSBA, xCLKAB, and
xCLKBA are powered by V
DDA
. All inputs are 5-volt tolerant.
Additionally, it is recommended that all unused inputs be tied
to V
SS
through a 1KΩ resistor. Input signal transitions should
be driven to the UT54ACS164646S with a rise and fall time
that is < 100ms.
POWER APPLICATION GUIDELINES
For proper operation connect power to all V
DDx
pins and
ground all V
SS
pins (i.e., no floating V
DDx
or V
SS
input pins).
By virtue of the UT54ACS164646S warm-spare feature, power
supplies V
DDB
and V
DDA
may be applied to the device in any
order. To ensure the device is in cold-spare mode, both sup-
plies, V
DDB
and V
DDA
, must be equal to V
SS
+/- 0.3V. Warm-
spare operation is in effect when one power supply is >1V and
the other power supply is equal to V
SS
+/- 0.3V. If V
DDB
has a
power-on ramp rate longer than 1 second, then V
DDA
should be
powered-on first to ensure proper control of xDIR and xOE.
During normal operation of the part, after power-up, ensure
V
DDB
> V
DDA
.
By definition, warm sparing occurs when half of the chip re-
ceives its normal VDD supply value while the VDD supplying
the other half of the chip is set to 0.0V. When the chip is ’warm
spared’, the side that has its VDD set to a normal operational
value is ’actively’ tristated because the chip’s internal OE sig-
nal is forced low. The side of the chip that has VDD set to 0.0V
is ’passively’ tristated by the cold spare circuitry.
In order to minimize transients and current consumption, the
user is encouraged to first apply a high level to the xOE pins
and then power down the appropriate supply.
FUNCTION TABLE
Inputs
xOE
X
X
H
H
L
L
L
L
+
xDIR
X
X
X
X
L
L
H
H
xCLKAB
↑
X
↑
H or L
X
X
X
H or L
xCLKBA
X
↑
↑
H or L
X
H or L
X
X
xSAB
X
X
X
X
X
X
L
H
xSBA
X
X
X
X
L
H
X
X
Data I/O
+
xA1-xA8
Input
Unspecified
Input
Input
Output
Output
Input
Input
xB1-xB8
Unspecified
Input
Input
Input
Input
Input
Output
Output
Store A, B unspecified
+
Store B, A unspecified
+
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Recall stored B data to A bus
Real-time A data to B Bus
Recall stored A data to B bus
Operation or Function
The data-output functions may be enabled or disabled by various signals xOE or xDIR. Data-input functions are always enabled, i.e. data at the bus terminals is
stored on every low-to-high transition of the clock inputs.
3
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL LET Threshold
SEU Onset LET Threshold
4
SEU Error Rate
2
Neutron Fluence
3
LIMIT
1.0E5
>110
>97 @4.5V, >74@ 3.0V
Immune @4.5V, 6.3E-10 @3.0V
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
errors/bit-day
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Adams 90% worst case particle environment, geosynchronous orbit, 100mils of Aluminum shielding
3. Not tested, inherent of CMOS technology.
4. Core logic is driven by
V
DDB.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/OB
(Port B)
2
V
I/OA
(Port A)
2
V
DDB
V
DDA
T
STG
T
J
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin
Voltage any pin
Supply voltage
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-0.3 to 6.0
-0.3 to 6.0
-0.3 to 6.0
-0.3 to 6.0
-65 to +150
+175
20
±10
250
UNITS
V
V
V
V
°C
°C
°C/W
mA
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For cold spare mode (V
DDx
= V
SS
+/- 0.3V), V
I/Ox
may be -0.3V to the maximum recommended operating V
DDx
+ 0.3V.
5
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