Standard Products
UT54ACTQ16244
RadHard CMOS 16-bit Buffer/Line Driver, TTL Inputs, and
Three-State Outputs
Preliminary Datasheet
November 3, 2006
www.aeroflex.com/radhard
FEATURES
16 non-inverting buffers with three-state outputs
Guaranteed simultaneously switching noise level and dy-
namic threshold performance
Separate control logic for each byte and nibble
0.6µm Commercial RadHard
TM
CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
High speed, low power consumption
Output source/sink 24mA
Standard Microcircuit Drawing 5962-06243
- QML compliant part
Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACTQ16244 buffer/line driver is built
using Aeroflex’s Commercial RadHard
TM
epitaxial CMOS
technology and is ideal for space applications. This high speed,
low power UT54ACTQ16244 buffer/line driver is designed to
improve the performance and density of three-state memory
address drivers, clock drivers, and bus-oriented receivers and
transmitters. The UT54ACTQ16244 can be used as four 4-bit
(nibble) buffers, two 8-bit (byte) buffers, or one 16-bit buffer.
The device provides true outputs and symmetrical OE (active-
low) output-enable inputs. The device is nibble controlled with
each nibble functioning identically, but independent of each oth-
er. The control pins can be shorted together to obtain full 16-bit
operation.
LOGIC SYMBOL
OE1
(1)
EN1
EN2
EN3
EN4
OE2 (48)
OE3 (25)
OE4 (24)
I0
I1
I2
(47)
(46)
(44)
(2)
1
1
1
(3)
(5)
(6)
1
2
(8)
(9)
(11)
(12)
(13)
(14)
(16)
(17)
1
4
(19)
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
(43)
I3
(41)
I4
(40)
I5
(38)
I6
(37)
I7
(36)
I8
(35)
I9
(33)
I10
(32)
I11
(30)
I12
(29)
I13
(27)
I14
(26)
I15
1
3
O12
(20)
O13
(22)
O14
(23)
O15
FUNCTION TABLE
PIN DESCRIPTION
Pin Names
OEn
I0-I15
O0-O15
Description
Output Enable Input (Active Low)
Inputs
Outputs
ENABLE
OE1, OE2,
OE3, OE4
L
L
H
Inputs
I0-I3, I4-I7,
I8-I11, I12-I16
L
H
X
Outputs
O0-O3, O4-07,
O8-O11, O12-O15
L
H
Z
1
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL Immune
SEU Onset Let
Neutron Fluence
2
LIMIT
1.0E5
>108
N/A
3
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
3. This device contains no memory storage elements which can be upset.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/O
V
DD
T
STG
T
J
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin during operation
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-.3 to V
DD
+.3
-0.3 to 6.0
-65 to +150
+175
20
±10
310
UNITS
V
V
°C
°C
°C/W
mA
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
t
INRISE
t
INFALL
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
Maximize input rise or fall time
(V
IN
transitioning betweenV
IL
(max) and V
IH
(min))
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
20
UNITS
V
V
°C
ns
4
DC ELECTRICAL CHARACTERISTICS
1
(-55°C < T
C
< +125°C)
SYMBOL
V
IL
V
IH
I
IN
PARAMETER
Low level input voltage
2
High level input voltage
2
Input leakage current
3
CONDITION
V
DD
from 4.5 to 5.5V
V
DD
from 4.5 to 5.5V
V
DD
from 4.5V to 5.5V
V
IN
= V
DD
or V
SS
I
OZ
Three-state output leakage current
3
V
DD
from 4.5V to 5.5V
V
IN
= V
DD
or V
SS
I
OS
Short-circuit output current
4, 5
V
O
= V
DD
or V
SS
V
DD
from 4.5V to 5.5V
V
OL1
Low-level output voltage
3, 6
I
OL
= 24mA
I
OL
= 24mA
I
OL
= 100µA
-55°C, 25°C
+125°C
-55°C, 25°C,
0.36
0.5
0.2
V
-600
600
mA
-10
10
µA
2.0
-1
1
MIN
MAX
0.8
UNIT
V
V
µA
V
DD
= 4.5V to 5.5V +125°C
V
OL2
Low-level output voltage
3, 6, 7
I
OL
= 50mA
V
IN
= 2.0V or 0.8V
V
DD
= 5.5V
V
OH1
High-level output voltage
3, 6
I
OH
= -24mA
I
OH
= -24mA
I
OH
= -100µA
+125°C
-55°C, 25°C
+125°C
-55°C, 25°C,
+125°C
V
DD
- 1.1
V
DD
- 1.3
0.4
1.5
V
V
V
DD
- 0.64
V
DD
- 0.8
V
DD
- 0.2
1.0
V
-55°C, 25°C
0.8
V
V
DD
= 4.5V to 5.5V
V
OH2
High-level output voltage
3, 6, 7
I
OH
= -50mA
V
IN
= 2.0V or 0.8V
V
DD
= 5.5V
V
IC
+
Positive input clamp voltage
-55°C, 25°C
+125°C
For input under test, I
IN
= 18mA
V
DD
= 0.0V
V
IC
-
Negative input clamp voltage
For input under test, I
IN
=-18mA
V
DD
= open
-1.5
-0.4
V
P
total
Power dissipation
8, 9, 10
C
L
= 20pF
V
DD
from 4.5V to 5.5V
1.0
mW/
MHz
5
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