EEWORLDEEWORLDEEWORLD

Part Number

Search

531MA92M0000DG

Description
LVPECL Output Clock Oscillator, 92MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531MA92M0000DG Overview

LVPECL Output Clock Oscillator, 92MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531MA92M0000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency92 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Maintenance of Fukang LPG dual fuel car
LPG (Liquefied Petroleum Gas) is an efficient, safe and clean alternative fuel for automobiles. It is the most mature low-pollution automobile fuel for promotion. The promotion and application of LPG ...
frozenviolet Automotive Electronics
GaN Power HEMT > 650 V: Parametric Analysis and Comparison with SiC MOSFET
Over the past few years, SiC MOSFETs have dominated high voltage (600V) and high power applications. Advantages such as thermal conductivity, high critical field, greatly improved switching efficiency...
兰博 RF/Wirelessly
Free e-contest format
[i=s]This post was last edited by paulhyde on 2014-9-15 09:40[/i] :P Everyone is welcome to express their opinions!...
flomingo Electronics Design Contest
stm32DMA peripheral address calculation problem
I would like to ask how the DMA peripheral address is calculated. For example, if ADC1 uses DMA1 channel 5, how is the data register address of ADC1 calculated? I checked the official manual, but it d...
2315862 stm32/stm8
Performance comparison of three classic wireless transceiver modules [ZT]
[i=s] This post was last edited by paulhyde on 2014-9-15 09:07 [/i] Performance comparison of three classic wireless transceiver modules The CC1100 module uses the CC1100 high-performance monolithic w...
yewen521 Electronics Design Contest
Voltage controlled current source composed of opa547
I want to use op07 and opa547 chips to form a voltage-controlled current source. The problem I encounter now is that the voltage at the positive and negative ends of opa547 are not equal. Why is this?...
alllllll Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2284  1374  1036  2739  925  46  28  21  56  19 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号