EEWORLDEEWORLDEEWORLD

Part Number

Search

531RA164M000DG

Description
LVPECL Output Clock Oscillator, 164MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531RA164M000DG Overview

LVPECL Output Clock Oscillator, 164MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531RA164M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency164 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Please tell me about the development details of AMCC 405EZ development board~
Has anyone developed on 405EZ Linux? I want to know how 405EZ Linux supports WME virtual machines and SMF. I hope experts can give me some advice!...
smartsheep Embedded System
How is "u8 Dat2:7;" written in the structure? What does it mean?
Look at the following program. What is the writing method of "u8 Dat2: 7;" and what does it mean? How can the structure be assigned values in this way? typedef struct {// u32 Dat : 23;// u32 S : 1;u8 ...
shijizai stm32/stm8
2015 TI Internet of Things Competition: Small Ball Explorer--EEWORLD University Hall
2015 TI Internet of Things Competition: Ball Explorer : https://training.eeworld.com.cn/course/2283[b][size=4]Work by the North University of China team: The spherical robot has a spherical shell, whi...
chenyy Robotics Development
eeworld group purchase activity TMP006 chip small test resources
, Arial, sans-serif][size=12px][color=#000][url=https://bbs.eeworld.com.cn/thread-372231-1-1.html]EEWorld Group Buying Activity TMP006 Chip Small Test Resources[/url][/color][/size][/font][/color][col...
蓝雨夜 Analogue and Mixed Signal
Modeling and Optimization Design of Finite State Machines
...
至芯科技FPGA大牛 FPGA/CPLD
Design of EMI filter for DC power supply
1 Design principle - meet the maximum impedance mismatch Insertion loss should be increased as much as possible, that is, signal reflection should be increased as much as possible. Assume that the out...
404846547 Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2763  905  2924  2817  2169  56  19  59  57  44 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号