552AF000207BG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 552AF000207BG

552AF000207BG: DescriptionLVPECL Output Clock Oscillator, 625MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size4MB，80 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

552AF000207BG Overview

LVPECL Output Clock Oscillator, 625MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

552AF000207BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	IT CAN ALSO OPERATE AT 622.08 MHZ
Maximum control voltage	3.3 V
Minimum control voltage
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	100 ppm
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	552
Installation features	SURFACE MOUNT
Nominal operating frequency	625 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	177.8mm x 127.0mm x 41.91mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

Si552

U A L

R E Q U E N C Y

VCXO (10 M H

Z T O

1.4 GH

)

Features

Available with any-rate output

frequencies from 10–945 MHz and

select frequencies to 1.4 GHz

Two selectable output frequencies

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL, LVDS

& CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications

SONET/SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical Modules

Clock and data recovery

Ordering Information:

See page 7.

Description

The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced

DSPLL

circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and select frequencies to 1400 MHz. Unlike traditional VCXO’s where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments typically found in communication

systems. The Si552 IC based VCXO is factory configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

Pin Assignments:

See page 6.

(Top View)

GND

CLK–

CLK+

Functional Block Diagram

CLK- CLK+

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 0.5 7/06

Si552

Recommended Resources

A brief discussion on the circuit diagram of electrical control

Infrared remote control receiving circuit for Panasonic TC-29P200G TV

Bidirectional frequency conversion circuit

Chopping method reverse bias circuit

Platinum resistance temperature sensor circuit

555 single variable dual power supply circuit

Regarding the problem of CAN communication output when the chip is sleeping: I would like to ask everyone, when the chip enters sleep (at this time CAN and related peripherals are enabled), it will cause the inability to send and receive for a while, even after the chip wakes ...; nt52241930 Microcontroller MCU

Infrared receiving circuit and waveform decoding: Infrared receiving circuit and waveform decoding...; fish001 Wireless Connectivity

No CES in PCB: I have newly installed Mentor Expedition 7.9.3. After opening Expedition PCB, I opened a board, but found that the CES on the Expedition PCB software is gray and cannot be used. What's going on? ? ? W...; sagacl1 PCB Design

OPEN1081----Download UBOOT\wifi driver: I received the development board from Qingke on Monday. I didn't expect that there were so many modules that might not be used in the project I chose. If I had known earlier, I could have set up a pro...; bx_zyd RF/Wirelessly

A lifelong test: You are driving a car. On a stormy night. You pass a bus station. There are three people waiting for the bus. One is a dying old man, so pitiful. One is a doctor, he once saved your life, he is a grea...; kangyun Talking

LM311 peak detection circuit (TI): I've been working on a peak detection circuit recently. I found it online. The classic one is the LM311. I just happened to have it on hand! I built one according to the datasheet, but it didn't work ...; 汉江之源 51mcu

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components