A29L004A Series
512K X 8 Bit CMOS 3.0 Volt-only,
Preliminary
Document Title
512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev.
0.0
Boot Sector Flash Memory
History
Initial issue
Issue Date
March 9, 2005
Remark
Preliminary
PRELIMINARY
(March, 2005, Version 0.0)
AMIC Technology, Corp.
A29L004A Series
512K X 8 Bit CMOS 3.0 Volt-only,
Preliminary
Features
Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write
operations for compatibility with high performance 3.3
volt microprocessors
Access times:
- 70/90 (max.)
Current:
- 4 mA typical active read current
- 20 mA typical program/erase current
-
200 nA typical CMOS standby
-
200 nA Automatic Sleep Mode current
Flexible sector architecture
-
16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that
sector. Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
Top or bottom boot block configurations available
Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
-
Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
-
Superior inadvertent write protection
Data
Polling and toggle bits
-
Provides a software method of detecting completion of
program or erase operations
Ready /
BUSY
pin (RY /
BY
)
- Provides a hardware method of detecting completion of
program or erase operations (not available on 32-pin
PLCC & (s)TSOP packages)
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin (
RESET
)
-
Hardware method to reset the device to reading array
data (not available on 32 pin PLCC & (s)TSOP
packages)
Package options
-
40-pin TSOP (forward type), 32-pin PLCC or (s)TSOP
(forward type)
Boot Sector Flash Memory
General Description
The A29L004A is a 4Mbit, 3.0 volt-only Flash memory
organized as 524,288 bytes of 8 bits. The 8 bits of data
appear on I/O
0
- I/O
7
. The A29L004A is offered in 40-pin
TSOP, 32-pin PLCC or (s)TSOP packages. This device is
designed to be programmed in-system with the standard
system 3.0 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However,
the A29L004A can also be programmed in standard EPROM
programmers.
The A29L004A has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O
6
toggle bit, the
A29L004A has a second toggle bit, I/O
2
, to indicate whether
the addressed sector is being selected for erase. The
A29L004A also offers the ability to program in the Erase
Suspend mode. The standard A29L004A offers access times
of 70 and 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
device has separate chip enable (
CE
), write enable (
WE
)
and output enable (
OE
) controls.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
PRELIMINARY
(March, 2005, Version 0.0)
1
The A29L004A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY /
BY
pin (not
AMIC Technology, Corp.
A29L004A Series
available on 32-pin PLCC & (s)TSOP), or by reading the I/O
7
(
Data
Polling) and I/O
6
(toggle) status bits. After a program
or erase cycle has been completed, the device is ready to
read array data or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L004A is fully erased
when shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware
RESET
pin terminates any operation in
progress and resets the internal state machine to reading
array data (not available on 32-pin PLCC & (s)TSOP). The
RESET
pin may be tied to the system reset circuitry. A
system reset would thus also reset the device, enabling the
system microprocessor to read the boot-up firmware from the
Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Pin Configurations
40-pin TSOP
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
A17
VSS
NC
NC
A10
I/O
7
I/O
6
I/O
5
I/O
4
VCC
VCC
NC
I/O
3
I/O
2
I/O
1
I/O
0
OE
VSS
CE
A0
A29L004AW
32
31
30
29
28
27
26
25
24
23
22
21
PLCC
32-pin TSOP (8mm X 20mm)
32-pin sTSOP (8mm X 13.4mm)
32-pin sTSOP (8mm X 14mm)
VCC
A16
A18
A17
WE
A12
A15
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
28
27
A14
A13
A8
A9
A11
OE
A10
CE
I/O
7
A29L004AL
26
25
24
23
22
21
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A29L004AV (8mm X 20mm)
A29L004AX (8mm X 13.4mm)
A29L004AY (8mm X 14mm)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A0
A1
A2
A3
32
31
I/O
5
GND
I/O
2
I/O
3
I/O
4
I/O
1
I/O
6
30
4
3
2
1
PRELIMINARY
(March, 2005, Version 0.0)
2
AMIC Technology, Corp.
A29L004A Series
Block Diagram
RY/BY (N/A 32-pin PLCC, (s)TSOP)
VCC
VSS
Sector Switches
Erase Voltage
Generator
State
Control
WE
Command
Register
CE
OE
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
Input/Output
Buffers
I/O
0
- I/O
7
RESET
(N/A 32-pin PLCC,
(s)TSOP)
STB
VCC Detector
Timer
Address Latch
Y-Decoder
Y-Gating
A0-A18
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 - A18
I/O
0
- I/O
7
Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable
Output Enable
Hardware Reset (N/A 32-pin PLCC, (s)TSOP)
Ready/
BUSY
- Output (N/A 32-pin PLCC, (s)TSOP)
Ground
Power Supply
Pin not connected internally
Description
CE
WE
OE
RESET
RY/
BY
VSS
VCC
NC
PRELIMINARY
(March, 2005, Version 0.0)
3
AMIC Technology, Corp.
A29L004A Series
Absolute Maximum Ratings*
Storage Temperature Plastic Packages . …… .0°C to + 70°C
Ambient Temperature with Power Applied…… 0°C to + 70°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . …... . . . -0.5V to +4.0V
A9,
OE
&
RESET
(Note 2) . . . . . . . . . . ….. . -0.5 to +12.5V
All other pins (Note 1) . . . . . . . . . . . ….. -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . ….. … 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0V
for periods up to 20ns.
2. Minimum DC input voltage on A9,
OE
and
RESET
is -
0.5V. During voltage transitions, A9,
OE
and
RESET
may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns. (
RESET
is
N/A on 32-pin PLCC & (s)TSOP)
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . ….. . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . ….. . . +2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29L004A Device Bus Operations
Operation
CE
L
L
VCC
±
0.3 V
L
X
L
L
X
OE
L
H
X
H
X
H
H
X
WE
H
L
X
H
X
L
L
X
RESET
(N/A 32-pin PLCC, (s)TSOP)
H
H
VCC
±
0.3 V
H
L
V
ID
V
ID
V
ID
A0 – A18
I/O
0
- I/O
7
Read
Write
CMOS Standby
Output Disable
Hardware Reset
Sector Protect
(See Note 2)
Sector Unprotect
(See Note 2)
Temporary Sector
Unprotect
A
IN
A
IN
X
X
X
Sector Address,
A6=L, A1=H, A0=L
Sector Address,
A6=H, A1=H, A0=L
A
IN
D
OUT
D
IN
High-Z
High-Z
High-Z
D
IN
D
IN
D
IN
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5V, X = Don't Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Notes:
1. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.
2. This function is not available on 32-pin PLCC & (s)TSOP packages.
PRELIMINARY
(March, 2005, Version 0.0)
4
AMIC Technology, Corp.
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