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XC2V500-6FG456C

Description
FPGA, 768 CLBS, 500000 GATES, 750 MHz, PBGA256
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,318 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Download Datasheet Parametric View All

XC2V500-6FG456C Overview

FPGA, 768 CLBS, 500000 GATES, 750 MHz, PBGA256

XC2V500-6FG456C Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerXILINX
Parts packaging codeBGA
package instruction23 X 23 MM, 1 MM PITCH, MO-034AAJ-1, FBGA-456
Contacts456
Reach Compliance Code_compli
ECCN codeEAR99
maximum clock frequency820 MHz
Combined latency of CLB-Max0.35 ns
JESD-30 codeS-PBGA-B456
JESD-609 codee0
length23 mm
Humidity sensitivity level3
Configurable number of logic blocks768
Equivalent number of gates500000
Number of entries264
Number of logical units6912
Output times264
Number of terminals456
Maximum operating temperature85 °C
Minimum operating temperature
organize768 CLBS, 500000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA456,22X22,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)225
power supply1.5,1.5/3.3,3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height2.6 mm
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width23 mm
Base Number Matches1
1
R
Virtex-II Platform FPGAs:
Complete Data Sheet
Product Specification
DS031 (v3.5) November 5, 2007
Module 1:
Introduction and Overview
7 pages
Summary of Features
General Description
Architecture
Device/Package Combinations and Maximum I/O
Ordering Examples
Module 3:
DC and Switching Characteristics
43 pages
Electrical Characteristics
Performance Characteristics
Switching Characteristics
Pin-to-Pin Output Parameter Guidelines
Pin-to-Pin Input Parameter Guidelines
DCM Timing Parameters
Source-Synchronous Switching Characteristics
Module 2:
Functional Description
41 pages
Detailed Description
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Input/Output Blocks (IOBs)
Digitally Controlled Impedance (DCI)
Configurable Logic Blocks (CLBs)
18-Kb Block SelectRAM™ Resources
18-Bit x 18-Bit Multipliers
Global Clock Multiplexer Buffers
Digital Clock Manager (DCM)
Module 4:
Pinout Information
226 pages
Pin Definitions
Pinout Tables
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CS144/CSG144 Chip-Scale BGA Package
FG256/FGG256 Fine-Pitch BGA Package
FG456/FGG456 Fine-Pitch BGA Package
FG676/FGG676 Fine-Pitch BGA Package
BG575/BGG575 Standard BGA Package
BG728/BGG728 Standard BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
BF957Flip-Chip BGA Package
Routing
Creating a Design
Configuration
IMPORTANT NOTE:
Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
© 2000–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS031 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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