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XC2S50E-6TQG144I

Description
Field Programmable Gate Array, 384 CLBs, 23000 Gates, 357MHz, 1728-Cell, CMOS, PQFP144, LEAD FREE, PLASTIC, TQFP-144
CategoryProgrammable logic devices    Programmable logic   
File Size886KB,108 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Environmental Compliance  
Download Datasheet Parametric View All

XC2S50E-6TQG144I Overview

Field Programmable Gate Array, 384 CLBs, 23000 Gates, 357MHz, 1728-Cell, CMOS, PQFP144, LEAD FREE, PLASTIC, TQFP-144

XC2S50E-6TQG144I Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid2024226996
Parts packaging codeQFP
package instructionLEAD FREE, PLASTIC, TQFP-144
Contacts144
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresMAXIMUM USABLE GATES = 50000
maximum clock frequency357 MHz
Combined latency of CLB-Max0.47 ns
JESD-30 codeS-PQFP-G144
JESD-609 codee3
length20 mm
Humidity sensitivity level3
Configurable number of logic blocks384
Equivalent number of gates23000
Number of entries182
Number of logical units1728
Output times182
Number of terminals144
organize384 CLBS, 23000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP144,.87SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width20 mm
0
R
Spartan-IIE FPGA Family
Data Sheet
0
0
Product Specification
DS077 June 18, 2008
This document includes all four modules of the Spartan
®
-IIE FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS077-1 (v2.3) June 18, 2008
Introduction
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 3:
DC and Switching Characteristics
DS077-3 (v2.3) June 18, 2008
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
- Configuration Switching Characteristics
Module 2:
Functional Description
DS077-2 (v2.3) June 18, 2008
Architectural Description
- Spartan-IIE Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
Module 4:
Pinout Tables
DS077-4 (2.3) June 18, 2008
Pin Definitions
Pinout Tables
IMPORTANT NOTE:
The Spartan-IIE FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2003-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077 June 18, 2008
Product Specification
www.xilinx.com
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