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XC2S400E-6PQG208C

Description
FPGA, 864 CLBS, 52000 GATES, 357 MHz, PBGA256
Categorysemiconductor    Programmable logic devices   
File Size886KB,108 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Download Datasheet Parametric View All

XC2S400E-6PQG208C Overview

FPGA, 864 CLBS, 52000 GATES, 357 MHz, PBGA256

XC2S400E-6PQG208C Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals256
Maximum operating temperature85 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage1.89 V
Minimum supply/operating voltage1.71 V
Rated supply voltage1.8 V
Processing package descriptionFBGA-256
stateACTIVE
packaging shapeSQUARE
Package SizeGRID ARRAY
surface mountYes
Terminal formBALL
Terminal spacing1 mm
terminal coatingTIN LEAD
Terminal locationBOTTOM
Packaging MaterialsPLASTIC/EPOXY
Temperature levelCOMMERCIAL EXTENDED
organize864 CLBS, 52000 GATES
Maximum FCLK clock frequency357 MHz
Number of configurable logic modules864
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits52000
The maximum delay of a CLB module0.4700 ns
0
R
Spartan-IIE FPGA Family
Data Sheet
0
0
Product Specification
DS077 June 18, 2008
This document includes all four modules of the Spartan
®
-IIE FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS077-1 (v2.3) June 18, 2008
Introduction
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 3:
DC and Switching Characteristics
DS077-3 (v2.3) June 18, 2008
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
- Configuration Switching Characteristics
Module 2:
Functional Description
DS077-2 (v2.3) June 18, 2008
Architectural Description
- Spartan-IIE Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
Module 4:
Pinout Tables
DS077-4 (2.3) June 18, 2008
Pin Definitions
Pinout Tables
IMPORTANT NOTE:
The Spartan-IIE FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2003-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077 June 18, 2008
Product Specification
www.xilinx.com
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