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XC2S200E-6FG456I

Description
Field Programmable Gate Array, 864 CLBs, 52000 Gates, 357MHz, 5292-Cell, CMOS, PBGA456, FBGA-456
CategoryProgrammable logic devices    Programmable logic   
File Size886KB,108 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Download Datasheet Parametric View All

XC2S200E-6FG456I Overview

Field Programmable Gate Array, 864 CLBs, 52000 Gates, 357MHz, 5292-Cell, CMOS, PBGA456, FBGA-456

XC2S200E-6FG456I Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Objectid1940877962
Parts packaging codeBGA
package instructionFBGA-456
Contacts456
Reach Compliance Codenot_compliant
ECCN code3A991.D
Other featuresMAXIMUM USABLE GATES = 150000
maximum clock frequency357 MHz
Combined latency of CLB-Max0.47 ns
JESD-30 codeS-PBGA-B456
JESD-609 codee0
length23 mm
Humidity sensitivity level3
Configurable number of logic blocks864
Equivalent number of gates52000
Number of entries289
Number of logical units5292
Output times289
Number of terminals456
organize864 CLBS, 52000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA456,22X22,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)225
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height2.6 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width23 mm
0
R
Spartan-IIE FPGA Family
Data Sheet
0
0
Product Specification
DS077 June 18, 2008
This document includes all four modules of the Spartan
®
-IIE FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS077-1 (v2.3) June 18, 2008
Introduction
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 3:
DC and Switching Characteristics
DS077-3 (v2.3) June 18, 2008
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
- Configuration Switching Characteristics
Module 2:
Functional Description
DS077-2 (v2.3) June 18, 2008
Architectural Description
- Spartan-IIE Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
Module 4:
Pinout Tables
DS077-4 (2.3) June 18, 2008
Pin Definitions
Pinout Tables
IMPORTANT NOTE:
The Spartan-IIE FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2003-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS077 June 18, 2008
Product Specification
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