QL8150-8PF144M datasheet, PDF - EEWORLD Datasheet

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QL8150-8PF144M: DescriptionField Programmable Gate Array, 640 CLBs, 188946 Gates, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MO-136BT, TQFP-144; CategoryProgrammable logic devices Programmable logic; File Size2MB，96 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL8150-8PF144M Overview

Field Programmable Gate Array, 640 CLBs, 188946 Gates, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MO-136BT, TQFP-144

QL8150-8PF144M Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MO-136BT, TQFP-144
Contacts	144
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Combined latency of CLB-Max	1.2936 ns
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
length	20 mm
Humidity sensitivity level	3
Configurable number of logic blocks	640
Equivalent number of gates	188946
Number of terminals	144
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	640 CLBS, 188946 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm
Base Number Matches	1

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Eclipse II Family Data Sheet

• • • • • •

Ultra-Low Power FPGA Combining Performance, Density, and

Embedded RAM

Device Highlights

Flexible Programmable Logic

• As low as 14 µA standby current

• 0.18 µm, six layer metal CMOS process

• 1.8 V VCC, 1.8/2.5/3.3 V drive capable I/O

• Up to 4,002 dedicated flip-flops

• Up to 55.3 K embedded SRAM bits

• Up to 310 I/O

• Up to 335 user available pins

• Up to 320 K system gates

• IEEE 1149.1 boundary scan testing compliant

Advanced Clock Network

• Multiple dedicated low skew clock networks

• High drive input-only networks

• Quadrant-based segmentable clock networks

• User programmable Phase Locked Loops (PLL)

Embedded Computational Units

(ECUs)

Hardwired DSP building blocks with integrated

Multiply, Add, and Accumulate functions.

Security Features

The QuickLogic products come with secure

ViaLink® technology that protects intellectual

property from design theft and reverse engineering.

No external configuration memory needed;

instant-on at power-up.

Figure 1: Eclipse II Block Diagram

PLL

Embedded RAM Blocks

Embeded Computational Units

PLL

Embedded Dual Port SRAM

• Up to twenty-four 2,304 bit dual port high

performance SRAM blocks

• RAM/ROM/FIFO wizard for automatic

configuration

• Configurable and cascadable aspect ratio

Programmable I/O

• High performance I/O cell

• Programmable slew rate control

• Programmable I/O standards:

LVTTL, LVCMOS, LVCMOS18, PCI, GTL+,

SSTL2, and SSTL3

Independent I/O banks capable of supporting

multiple standards in one device

I/O register configurations: Input, Output,

Output Enable (OE)

PLL

Fabric

Embedded RAM Blocks

PLL

www.quicklogic.com

•

Eclipse II Family Data Sheet Rev. Q

Figure 4: Cascaded RAM Modules

WDATA

WADDR

RAM

Module

(2,304 bits)

RDATA

RADDR

WDATA

RAM

Module

(2,304 bits)

RDATA

The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ

and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE

ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths

of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some

higher order data or address lines may not be used.

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts

as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for

asynchronous READ operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by

connecting corresponding address lines together and dividing the words between modules.

A similar technique can be used to create depths greater than 256 words. In this case address signals higher

than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs

are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with

data from an external PROM (typically for ROM functions).

Embedded Computational Unit (ECU)

Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—

these functions require high logic cell usage while garnering only moderate performance results.

The Eclipse II architecture allows for functionality above and beyond that achievable using programmable logic

devices. By embedding a dynamically reconfigurable computational unit, the Eclipse II device can address

various arithmetic functions efficiently. This approach offers greater performance and utilization than

traditional programmable logic implementations. The embedded block is implemented at the transistor level

as shown in

Figure 5.

www.quicklogic.com

•

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