XRT86SH221
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
AUGUST 2008
REV. 1.0.1
GENERAL DESCRIPTION
The XRT86SH221 (Voyager-Lite) is a physical layer
SDH to PDH mapper/demapper which enables E1
aggregation to STM-1 via standard VC-12 to AU-3
and TUG-3/AU-4 mapping protocols. Voyager-Lite
supports all the framing, mapping and grooming
functions required for STM-1 mapper applications.
The device generates and terminates all SDH
Regenerator Section, Multiplexer Section and Path
Overhead including the low-order Virtual Container
(VC) Path Overhead. E1 framing is transparent;
therefore, the device neither generates nor
terminates the E1 frame.
F
IGURE
1. S
IMPLIFIED
B
LOCK
D
IAGRAM
SDH OH
Drop
VC-4 POH
Drop
A single Voyager-Lite performs mapping of 21
asynchronous E1 spans to either VC-12/TU-12/TUG-
2/ VC-3/AU-3/STM-0 or VC-12/TU-12/TUG-2/TUG-3/
STM-0. Mapping to STM-1 requires (3) Voyager-Lite
devices with one acting as "master" framer and two
acting as "slave" framers. In this configuration,
Voyager-Lite performs all the necessary framing,
pointer processing and mapping functions required
for mapping of 63xE1 spans to either VC-12/TU-12/
TUG-2/VC-3/AU-3/STM-1 or VC-12/TU-12/TUG-2/
TUG-3/VC-4/AU-4/STM-1 as shown in the block
diagram.
19.44Mhz
8kHz
STM-1 SOH
Processor
Master
Slave
XRT86SH221 Voyager Lite
Telecom
Bus
Rx
Telecom Bus or
Serial Port
Interface
Telecom
Bus
Tx
SDH
Trans-
Port
Proc
(SOH)
Rx
SDH
Path
Proc
(POH)
TU-12
To
TUG2
Rx
VC-12
Mapper
+
TU-12
Pointer
Proc
Rx
VC-12
Cross
Connect
21x21
Rx
21 Ch
E1
Frame
Sync
Bit
Retimer
21 Ch
E1
Short
Haul
LIU
Tx
Egress
SDH
Trans-
Port
Proc
(SOH)
Tx
VC3/
AU3
TUG3/
VC4/
AU4
Tx
VC-12
Mapper
+
TU-12
Pointer
Proc
Tx
VC-12
Cross
Connect
21x21
Tx
21 Ch
E1
Short
Haul
LIU
Rx
Ingress
Recovered
Line Clock
STM-1 SOH
Processor
PLL
E1, 2xE1
4xE1, 8xE1
JTAG
Microprocessor
SDH OH
Add
VC-4 P OHSingle Input
Clock
Add
Reference
JTAG
Port
Microprocessor
Interface
PACKAGE ORDERING INFORMATION
P
RODUCT
N
UMBER
XRT86SH221IB
P
ACKAGE
T
YPE
388 PBGA
O
PERATING
T
EMPERATURE
R
ANGE
-40° to +85°
C
C
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT86SH221
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. 1.0.1
FEATURES
VT Mapper
•
Maps up to 21 synchronous or asynchronous E1 signals to SDH AU-3 via TUG-2 and TU-12, or to SDH
STM-0 payload capacity via VT Groups and VT2.
•
Dynamic VT/TU size selection.
•
Inserts valid V5 bit interleaved parity BIP-2 in the transmit direction.
•
Detects and counts V5 BIP-2 errors for performance monitoring.
•
Configurable remote error indication REI-V insertion for V5 BIP-2 errors.
•
Supports proprietary V5 remote loopcodes.
•
Detects and counts remote errors.
•
Automatic receive monitor functions include VT/TU remote defect indication RDI-V, VT/TU remote failure
indication RFI-V, VT/TU remote error indication REI-V, BIP-2 errors, VT/TU AIS, VT/TU Automatic Protection
Switching (APS) signalling for low order path level, and VT/TU loss of pointer LOP-V.
•
Automatic receive monitoring functions can be configured to provide an interrupt to the control system, or the
device can be operated in a polled mode.
•
Test pattern generation and detection/dropping for setup and maintenance.
•
User configurable for VT/TU label, AIS-V, RDI-V, RFI-V, REI-V, APS, force BIP-2 errors, or unequipped
tributary insertion.
E1 Receive Framing Synchronizer
•
Provides a standard compliant 2.048 Mbits PCM30 CRC-4 E1 framer.
•
Provides off-line framer.
•
Complies with standards such as: ITU-T G.703, G.704, G.706 (including Annex B), G.732, G.735, G.736,
G.737, G.761, G.823, I.431 and ETS 300 011, 300 233.
•
Supports FAS, Signaling Multiframe, and CRC-4 framing structure.
•
FAS reframe time is 625µs maximum.
•
Provides Loss Of Frame (LOF), Loss of Multiframe detection.
•
Provides Change Of Frame Alignment (COFA) detection.
•
Provides Change Of signaling MultiFrame Alignment (COMFA) detection.
•
Provides a 2-frame slip buffer for bit retiming.
2
XRT86SH221
REV. 1.0.1
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
SDH Transmitter
•
Performs standard STM-0/STM-1 transmit processing.
•
Conforms to ITU-T I.432, ANSI T1.105, and Bellcore-253
•
Provides a 51.84MHz STM-0 serial interface or 6MHz / 19MHz 8-bit STM-0 / STM-1 parallel interface.
•
Performs SDH frame insertion and accepts external frame synchronization.
•
Performs optional transmit data scrambling.
•
Performs POH, SDH OH generation/insertion.
•
Generates transmit payload pointer (H1, H2) (fixed at 522) with NDF insertion.
•
Inserts A1/A2 with optional error mask.
•
Computes and inserts BIP-8 (B1, B2) with optional error mask.
•
Generates AIS-L, REI-L and RDI-L according to receiver state with option of SW or HW insertion.
•
Inserts LOS, forces SEF by software.
•
Generates RDI-P and REI-P automatically with optional SW or HW override.
•
Inserts fixed-stuff columns, calculates and inserts B3 error code.
SDH Receiver
•
Performs standard STM-0/STM-1 receive processing.
•
Conforms to ITU-T I.432, ANSI T1.105, and Bellcore-253.
•
Provides fully programmable threshold detection for SD and SF conditions.
•
Provides a 51.84MHz STM-0 serial interface or 6MHz / 19MHz 8-bit STM-0 / STM-1 parallel interface.
•
Provides section trace buffer with mismatch detection and invalid message detection.
•
Performs SDH frame synchronization.
•
Supports NDF, positive stuff and negative stuff for pointer processor.
•
Performs receive data de-scrambling.
•
Performs POH, SDH OH interpretation/extraction.
•
Interprets payload pointer (H1, H2).
•
Detects Out Of Frame (OOF), Loss Of Frame (LOF), Loss Of Signal (LOS), APS failure.
•
Detects Line Alarm Indication(L-AIS), Line remote Defect Indication (L-RDI), Loss Of Pointer.
•
Detects Path Alarm Indication, Path remote Defect Indication, Path extended RDI.
•
Provides signal label monitor with PLM detection.
•
Supports path trace buffer with TIM-P and invalid message detection.
•
Computes and compares B3, REI-L and REI-P errors.
•
Computes and compares BIP-8 (B1, B2) and counts the errors.
3
XRT86SH221
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................ 1
F
IGURE
1. S
IMPLIFIED
B
LOCK
D
IAGRAM
............................................................................................................................................ 1
P
ACKAGE
O
RDERING
I
NFORMATION
...................................................................................................... 1
FEATURES ........................................................................................................................ 2
TABLE OF CONTENTS......................................................................................................
I
1.0 PIN DESCRIPTIONS ................................................................................................................................ 4
1.1 MICROPROCESSOR INTERFACE PINS............................................................................................................ 4
1.2 BOUNDARY SCAN AND OTHER TEST PINS.................................................................................................... 6
1.3 GENERAL PURPOSE INPUT AND OUTPUT PINS............................................................................................ 7
1.4 TIMING AND CLOCK SIGNALS.......................................................................................................................... 7
1.5 LOW SPEED LINE INTERFACE SIGNALS ........................................................................................................ 9
1.6 HIGH SPEED SERIAL INTERFACE.................................................................................................................. 12
1.7 HIGH SPEED TELECOM BUS INTERFACE.................................................................................................... 13
1.8 HIGH SPEED SECTION AND PATH OVERHEAD BUS ................................................................................... 15
1.9 HIGH SPEED TU POH OVERHEAD BUS ......................................................................................................... 16
1.10 POWER AND GROUND PINS ......................................................................................................................... 18
2.0 APPLICATIONS AND PHYSICAL INTERFACE GENERAL OVERVIEW............................................. 20
F
IGURE
2. A
PPLICATION
D
IAGRAM
.................................................................................................................................................. 20
2.1 PHYSICAL INTERFACE .................................................................................................................................... 21
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
P
HYSICAL
I
NTERFACE
............................................................................................. 21
2.2 TELECOM BUS INTERFACE ............................................................................................................................ 22
F
IGURE
4. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
T
ELECOM
B
US
I
NTERFACE
...................................................................................... 22
2.3 STM-0 SERIAL INTERFACE SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE....................... 23
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
S
ERIAL
P
ORT
I
NTERFACE
....................................................................................... 23
2.4 SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE ...................................................................... 24
F
IGURE
6. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
SDH F
RAME
S
YNCHRONIZATION
............................................................................. 24
2.5 SDH OVERHEAD ADD-DROP INTERFACES .................................................................................................. 25
F
IGURE
7. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
SDH O
VERHEAD
A
DD
-D
ROP
I
NTERFACE
................................................................. 25
2.6 E1 SHORT HAUL LINE INTERFACE ................................................................................................................ 26
2.7 E1 TIMING INTERFACE .................................................................................................................................... 27
2.8 MICROPROCESSOR INTERFACE ................................................................................................................... 27
3.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 28
F
IGURE
8. F
UNCTIONAL
B
LOCK
D
IAGRAM
........................................................................................................................................ 28
3.1 INGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................. 29
F
IGURE
9. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
I
NGRESS
D
ATA
P
ATH
.............................................................................................. 29
3.2 E1 RECEIVE LIU (RXE1LIU) .............................................................................................................................
3.3 TRANSMIT LOW-ORDER (TU) OVERHEAD INSERTION BUS (TXTUPOH) ..................................................
3.4 VC-12/TU-12 TRANSMIT LOW-ORDER MAPPER AND OVERHEAD PROCESSOR (TXLOPOHPROC)......
3.5 VC-12 TRANSMIT CROSS-CONNECT (TXVC12XC) .......................................................................................
3.6 TRANSMIT SDH SOH/POH INSERTION BUS (TXOH) ....................................................................................
3.7 SDH TRANSMIT MAPPER AND PATH OVERHEAD PROCESSOR (TXPOHPROC) .....................................
3.8 SDH TRANSMIT FRAMER AND SECTION OVERHEAD PROCESSOR (TXSOHPROC)...............................
3.9 TRANSMIT TELECOM BUS (TXTBUS) ............................................................................................................
3.10 EGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................
29
29
30
30
30
31
32
33
34
F
IGURE
10. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
E
GRESS
D
ATA
P
ATH
............................................................................................ 34
3.11 RECEIVE TELECOM BUS (RXTBUS)............................................................................................................. 34
3.12 SDH RECEIVE FRAMER AND SECTION OVERHEAD PROCESSOR (RXSOHPROC) ............................... 35
3.13 SDH RECEIVE MAPPER AND PATH OVERHEAD PROCESSOR (RXPOHPROC) ..................................... 36
4.0 VOYAGER-LITE HARDWARE ARCHITECTURE AND ALGORITHMS ............................................... 37
F
IGURE
11. V
OYAGER
-L
ITE
A
RCHITECTURE
.................................................................................................................................... 37
4.1 MULTIPLEXING STRUCTURE.......................................................................................................................... 38
F
IGURE
12. M
ULTIPLEXING STRUCTURE
.......................................................................................................................................... 38
4.2 FUNCTIONAL BLOCKS .................................................................................................................................... 39
4.3 SDH TRANSMIT DATA FLOW .......................................................................................................................... 39
F
IGURE
13. SDH T
RANSMITTER
G
ENERAL
S
TRUCTURE
................................................................................................................... 40
4.4 SDH RECEIVE DATA FLOW............................................................................................................................. 40
F
IGURE
14. G
ENERAL
C
OMPOSITION OF A
SDH STM-N R
ECEIVER
................................................................................................. 41
4.5 VT MAPPER...................................................................................................................................................... 41
I
XRT86SH221
REV. 1.0.1
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
F
IGURE
15. T
OP
L
EVEL
B
LOCK
D
IAGRAM
........................................................................................................................................ 42
4.6 INTERRUPTS AND STATUS ............................................................................................................................ 43
F
IGURE
16. I
NTERRUPT
H
IERARCHY
............................................................................................................................................... 43
4.7 INTERRUPT PROCESSING AND CONTROL .................................................................................................. 44
4.8 STM-0/1 RECEIVE TRANSPORT PROCESSOR.............................................................................................. 44
F
IGURE
17. BYTE_ALIGN B
LOCK
F
UNCTIONAL
D
IAGRAM
.............................................................................................................. 44
T
ABLE
1: 16-
BYTE FRAME FOR
T
RAIL
API
D
..................................................................................................................................... 49
F
IGURE
18. R
ECEIVE
T
RACE
B
UFFER
M
EMORY
............................................................................................................................... 50
T
ABLE
2: A
DDRESSING
S
CHEME
U
SED TO
A
CCESS THE
SDH OH B
YTES
........................................................................................ 51
F
IGURE
19. R
ECEIVE
T
RANSPORT
O
VERHEAD
I
NTERFACE
T
IMING
................................................................................................... 52
STM-0/1 RECEIVE PATH PROCESSOR................................................................................................. 53
F
IGURE
20. P
OINTER
P
ROCESSING
FSM ........................................................................................................................................ 55
T
ABLE
3: SDH P
OINTER
E
VENT
T
YPES
.......................................................................................................................................... 55
F
IGURE
21. C
ONCATENATED
P
OINTER
I
NDICATOR
P
ROCESSING
FSM.............................................................................................. 57
T
ABLE
4: RDI-P S
ETTINGS AND
I
NTERPRETATION
........................................................................................................................... 58
T
ABLE
5: STS S
IGNAL
L
ABEL
M
ISMATCH
D
EFECT
C
ONDITIONS
....................................................................................................... 59
T
ABLE
6: T
RUTH
T
ABLE FOR
P
ATH
L
ABEL
E
RROR
C
ONDITIONS
....................................................................................................... 59
F
IGURE
22. P
ATH
O
VERHEAD
I
NTERFACE
T
IMING
............................................................................................................................ 62
F
IGURE
23. T
RANSMIT
T
RANSPORT
O
VERHEAD
I
NTERFACE
T
IMING
................................................................................................. 63
4.9 TELECOM BUS INTERFACE............................................................................................................................ 68
4.9.1 TRANSMIT TELECOM BUS .........................................................................................................................................
F
IGURE
24. T
RANSMIT
T
ELECOM
B
US
I
NTERFACE
T
IMING
................................................................................................................
4.9.2 2KHZ MODE IN STM-1 .................................................................................................................................................
F
IGURE
25. C1J1V1 P
ULSE IN
STM-1 2
K
H
Z
M
ODE
........................................................................................................................
4.9.3 RECEIVE TELECOM BUS ............................................................................................................................................
F
IGURE
26. R
ECEIVE
T
ELECOM
B
US
I
NTERFACE
T
IMING
..................................................................................................................
68
68
69
69
69
69
4.10 VT MAPPER .................................................................................................................................................... 71
F
IGURE
27. I
NTERNAL
B
US
S
TRUCTURE
......................................................................................................................................... 71
F
IGURE
28. M
ID
B
US
I
NTERFACE
.................................................................................................................................................... 73
F
IGURE
29. SDH
TO
VTM
DATA TRANSFER WITH ZERO POINTER OFFSET
......................................................................................... 73
F
IGURE
30. VTM
TO
SDH
DATA TRANSFER
.................................................................................................................................... 74
F
IGURE
31. E1 I
NTERFACE
T
IMING
(I
NTERNAL TO THE
C
HIP
) ........................................................................................................... 75
F
IGURE
32. E1 I
NTERFACE
T
IMING
(E1
SYNCHRONOUS MAPPING
, I
NTERNAL TO THE
C
HIP
)............................................................... 75
T
ABLE
7: V5 - VT P
ATH
E
RROR
C
HECKING
, S
IGNAL
L
ABEL AND
P
ATH
S
TATUS
................................................................................ 76
T
ABLE
8: N2
BYTE STRUCTURE
...................................................................................................................................................... 78
T
ABLE
9:
B
7-
B
8
MULTIFRAME STRUCTURE
....................................................................................................................................... 79
T
ABLE
10: S
TRUCTURE OF FRAMES
# 73 - 76
OF THE B
7-
B
8
MULTIFRAME
....................................................................................... 79
T
ABLE
11: K4 (
B
5-
B
7)
CODING AND INTERPRETATION
...................................................................................................................... 81
T
ABLE
12: Z7/K4 - VT P
ATH
G
ROWTH AND
VT P
ATH
R
EMOTE
D
EFECT
I
NDICATION
........................................................................ 81
F
IGURE
33. MKP (M
AKE
P
AYLOAD
),
ONE OF SEVEN
MKG : M
AKE
VT/TU G
ROUP
........................................................................... 82
F
IGURE
34. MKP (M
AKE
P
AYLOAD
), VT/TU G
ROUP
I
NTERLEAVING
................................................................................................. 83
F
IGURE
35. M
AKE
T
RIBUTARY
(MKT) ............................................................................................................................................. 84
F
IGURE
36. E
XTRACT
P
AYLOAD
(XTP) ........................................................................................................................................... 85
F
IGURE
37. R
EFERENCE
C
LOCKS
G
ENERATOR
(RCG).................................................................................................................... 86
DATA INTERFACE BETWEEN SDH/FRAMER AND MAPPER .............................................................. 87
F
IGURE
38. R
ECEIVE
SDH/F
RAMER
M
APPER
I
NTERFACE
................................................................................................................
F
IGURE
39. T
RANSMIT
SDH/F
RAMER
M
APPER
I
NTERFACE
..............................................................................................................
F
IGURE
40. E1 F
RAMER
S
YNCHRONIZATION
F
LOW
D
IAGRAM
..........................................................................................................
F
IGURE
41. F
LOW OF
CRC-4
MULTIFRAME ALIGNMENT FOR INTERWORKING
....................................................................................
87
87
88
90
4.11 E1 PHY LOOPBACK DIAGNOSTICS ............................................................................................................. 93
4.11.1 E1 LOOPBACKS......................................................................................................................................................... 93
F
IGURE
42. E1 F
ACILITY
L
OOPBACK
............................................................................................................................................... 93
4.11.2 E1 FACILITY I/O LOOPBACK .................................................................................................................................... 94
F
IGURE
43. E1 F
ACILITY
I/O L
OOPBACK
......................................................................................................................................... 94
4.11.3 E1 MODULE LOOPBACK ......................................................................................................................................... 95
F
IGURE
44. E1
MODULE
L
OOPBACK
................................................................................................................................................ 95
4.11.4 ALARM AND AUTO AIS ............................................................................................................................................. 96
F
IGURE
45. E1 A
UTO
AIS I
NSERTION
............................................................................................................................................. 96
T
ABLE
13: E1
TO
STM-0 -
RESPONSE TIME
< 125
US
..................................................................................................................... 96
T
ABLE
14: STM-0
TO
E1 -
RESPONSE TIME
< 125
USEC
................................................................................................................. 96
5.0 ANALOG FRONT END / LINE INTERFACE UNIT (LIU) SECTION...................................................... 98
F
IGURE
46. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
LIU S
ECTION
....................................................................................................... 98
5.1 TRANSMIT LINE INTERFACE UNIT................................................................................................................. 99
5.1.1 JITTER ATTENUATOR................................................................................................................................................. 99
5.1.2 TAOS (TRANSMIT ALL ONES).................................................................................................................................... 99
II
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