XRT86SH221 datasheet, PDF - EEWORLD Datasheet

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XRT86SH221: DescriptionDATACOM, FRAMER, PBGA388; CategoryTopical application Wireless rf/communication; File Size2MB，357 Pages; ManufacturerExar [Exar Corporation]

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XRT86SH221 Overview

DATACOM, FRAMER, PBGA388

XRT86SH221 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	388
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Rated supply voltage	1.8 V
Processing package description	27 × 27 MM, plastic, BGA-388
state	ACTIVE
packaging shape	SQUARE
Package Size	GRID array
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
Communication type	FRAMER

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XRT86SH221

SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU

AUGUST 2008

REV. 1.0.1

GENERAL DESCRIPTION

The XRT86SH221 (Voyager-Lite) is a physical layer

SDH to PDH mapper/demapper which enables E1

aggregation to STM-1 via standard VC-12 to AU-3

and TUG-3/AU-4 mapping protocols. Voyager-Lite

supports all the framing, mapping and grooming

functions required for STM-1 mapper applications.

The device generates and terminates all SDH

Regenerator Section, Multiplexer Section and Path

Overhead including the low-order Virtual Container

(VC) Path Overhead. E1 framing is transparent;

therefore, the device neither generates nor

terminates the E1 frame.

IGURE

1. S

IMPLIFIED

LOCK

IAGRAM

SDH OH

Drop

VC-4 POH

Drop

A single Voyager-Lite performs mapping of 21

asynchronous E1 spans to either VC-12/TU-12/TUG-

2/ VC-3/AU-3/STM-0 or VC-12/TU-12/TUG-2/TUG-3/

STM-0. Mapping to STM-1 requires (3) Voyager-Lite

devices with one acting as "master" framer and two

acting as "slave" framers. In this configuration,

Voyager-Lite performs all the necessary framing,

pointer processing and mapping functions required

for mapping of 63xE1 spans to either VC-12/TU-12/

TUG-2/VC-3/AU-3/STM-1 or VC-12/TU-12/TUG-2/

TUG-3/VC-4/AU-4/STM-1 as shown in the block

diagram.

19.44Mhz

8kHz

STM-1 SOH

Processor

Master

Slave

XRT86SH221 Voyager Lite

Telecom

Bus

Telecom Bus or

Serial Port

Interface

Telecom

Bus

SDH

Trans-

Port

Proc

(SOH)

SDH

Path

Proc

(POH)

TU-12

TUG2

VC-12

Mapper

TU-12

Pointer

Proc

VC-12

Cross

Connect

21x21

21 Ch

Frame

Sync

Bit

Retimer

21 Ch

Short

Haul

LIU

Egress

SDH

Trans-

Port

Proc

(SOH)

VC3/

AU3

TUG3/

VC4/

AU4

VC-12

Mapper

TU-12

Pointer

Proc

VC-12

Cross

Connect

21x21

21 Ch

Short

Haul

LIU

Ingress

Recovered

Line Clock

STM-1 SOH

Processor

PLL

E1, 2xE1

4xE1, 8xE1

JTAG

Microprocessor

SDH OH

Add

VC-4 P OHSingle Input

Clock

Add

Reference

JTAG

Port

Microprocessor

Interface

PACKAGE ORDERING INFORMATION

RODUCT

UMBER

XRT86SH221IB

ACKAGE

YPE

388 PBGA

PERATING

EMPERATURE

ANGE

-40° to +85°

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

•

(510) 668-7000

•

FAX (510) 668-7017

•

www.exar.com

XRT86SH221

SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU

REV. 1.0.1

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................ 1

IGURE

1. S

IMPLIFIED

LOCK

IAGRAM

............................................................................................................................................ 1

ACKAGE

RDERING

NFORMATION

...................................................................................................... 1

FEATURES ........................................................................................................................ 2

TABLE OF CONTENTS......................................................................................................

1.0 PIN DESCRIPTIONS ................................................................................................................................ 4

1.1 MICROPROCESSOR INTERFACE PINS............................................................................................................ 4

1.2 BOUNDARY SCAN AND OTHER TEST PINS.................................................................................................... 6

1.3 GENERAL PURPOSE INPUT AND OUTPUT PINS............................................................................................ 7

1.4 TIMING AND CLOCK SIGNALS.......................................................................................................................... 7

1.5 LOW SPEED LINE INTERFACE SIGNALS ........................................................................................................ 9

1.6 HIGH SPEED SERIAL INTERFACE.................................................................................................................. 12

1.7 HIGH SPEED TELECOM BUS INTERFACE.................................................................................................... 13

1.8 HIGH SPEED SECTION AND PATH OVERHEAD BUS ................................................................................... 15

1.9 HIGH SPEED TU POH OVERHEAD BUS ......................................................................................................... 16

1.10 POWER AND GROUND PINS ......................................................................................................................... 18

2.0 APPLICATIONS AND PHYSICAL INTERFACE GENERAL OVERVIEW............................................. 20

IGURE

2. A

PPLICATION

IAGRAM

.................................................................................................................................................. 20

2.1 PHYSICAL INTERFACE .................................................................................................................................... 21

IGURE

3. S

IMPLIFIED

LOCK

IAGRAM OF THE

HYSICAL

NTERFACE

............................................................................................. 21

2.2 TELECOM BUS INTERFACE ............................................................................................................................ 22

IGURE

4. S

IMPLIFIED

LOCK

IAGRAM OF THE

ELECOM

NTERFACE

...................................................................................... 22

2.3 STM-0 SERIAL INTERFACE SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE....................... 23

IGURE

5. S

IMPLIFIED

LOCK

IAGRAM OF THE

ERIAL

ORT

NTERFACE

....................................................................................... 23

2.4 SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE ...................................................................... 24

IGURE

6. S

IMPLIFIED

LOCK

IAGRAM OF THE

SDH F

RAME

YNCHRONIZATION

............................................................................. 24

2.5 SDH OVERHEAD ADD-DROP INTERFACES .................................................................................................. 25

IGURE

7. S

IMPLIFIED

LOCK

IAGRAM OF THE

SDH O

VERHEAD

-D

ROP

NTERFACE

................................................................. 25

2.6 E1 SHORT HAUL LINE INTERFACE ................................................................................................................ 26

2.7 E1 TIMING INTERFACE .................................................................................................................................... 27

2.8 MICROPROCESSOR INTERFACE ................................................................................................................... 27

3.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 28

IGURE

8. F

UNCTIONAL

LOCK

IAGRAM

........................................................................................................................................ 28

3.1 INGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................. 29

IGURE

9. S

IMPLIFIED

LOCK

IAGRAM OF THE

NGRESS

ATA

ATH

.............................................................................................. 29

3.2 E1 RECEIVE LIU (RXE1LIU) .............................................................................................................................

3.3 TRANSMIT LOW-ORDER (TU) OVERHEAD INSERTION BUS (TXTUPOH) ..................................................

3.4 VC-12/TU-12 TRANSMIT LOW-ORDER MAPPER AND OVERHEAD PROCESSOR (TXLOPOHPROC)......

3.5 VC-12 TRANSMIT CROSS-CONNECT (TXVC12XC) .......................................................................................

3.6 TRANSMIT SDH SOH/POH INSERTION BUS (TXOH) ....................................................................................

3.7 SDH TRANSMIT MAPPER AND PATH OVERHEAD PROCESSOR (TXPOHPROC) .....................................

3.8 SDH TRANSMIT FRAMER AND SECTION OVERHEAD PROCESSOR (TXSOHPROC)...............................

3.9 TRANSMIT TELECOM BUS (TXTBUS) ............................................................................................................

3.10 EGRESS DATA PATH FUNCTIONAL BLOCKS ............................................................................................

IGURE

10. S

IMPLIFIED

LOCK

IAGRAM OF THE

GRESS

ATA

ATH

............................................................................................ 34

3.11 RECEIVE TELECOM BUS (RXTBUS)............................................................................................................. 34

3.12 SDH RECEIVE FRAMER AND SECTION OVERHEAD PROCESSOR (RXSOHPROC) ............................... 35

3.13 SDH RECEIVE MAPPER AND PATH OVERHEAD PROCESSOR (RXPOHPROC) ..................................... 36

4.0 VOYAGER-LITE HARDWARE ARCHITECTURE AND ALGORITHMS ............................................... 37

IGURE

11. V

OYAGER

-L

ITE

RCHITECTURE

.................................................................................................................................... 37

4.1 MULTIPLEXING STRUCTURE.......................................................................................................................... 38

IGURE

12. M

ULTIPLEXING STRUCTURE

.......................................................................................................................................... 38

4.2 FUNCTIONAL BLOCKS .................................................................................................................................... 39

4.3 SDH TRANSMIT DATA FLOW .......................................................................................................................... 39

IGURE

13. SDH T

RANSMITTER

ENERAL

TRUCTURE

................................................................................................................... 40

4.4 SDH RECEIVE DATA FLOW............................................................................................................................. 40

IGURE

14. G

ENERAL

OMPOSITION OF A

SDH STM-N R

ECEIVER

................................................................................................. 41

4.5 VT MAPPER...................................................................................................................................................... 41

XRT86SH221 Related Products

	XRT86SH221	XRT86SH221_08
Description	DATACOM, FRAMER, PBGA388	DATACOM, FRAMER, PBGA388
Number of functions	1	1
Number of terminals	388	388
Maximum operating temperature	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel
Rated supply voltage	1.8 V	1.8 V
Processing package description	27 × 27 MM, plastic, BGA-388	27 × 27 MM, plastic, BGA-388
state	ACTIVE	ACTIVE
packaging shape	SQUARE	SQUARE
Package Size	GRID array	GRID array
surface mount	Yes	Yes
Terminal form	BALL	BALL
Terminal spacing	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Packaging Materials	Plastic/Epoxy	Plastic/Epoxy
Temperature level	INDUSTRIAL	INDUSTRIAL
Communication type	FRAMER	FRAMER

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