XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
SEPTEMBER 2008
REV. 1.0.2
GENERAL DESCRIPTION
The XRT73LC03A, 3-Channel, DS3/E3/STS-1 Line
Interface Unit is a low power CMOS version of the
XRT73L03A and consists of three independent line
transmitters and receivers integrated on a single chip
designed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73LC03A can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73LC03A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
•
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L03A
•
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
•
Contains a 4-Wire Microprocessor Serial Interface
•
Full Loop-Back Capability
•
Transmit and Receive Power Down Modes
•
Full Redundancy Support
•
Uses Minimum External components
•
Single +3.3V Power Supply
•
Low power CMOS design
•
5V tolerant I/O
•
-40°C to +85° Operating Temperature Range
C
•
Available in a 120 pin LQFP package
APPLICATIONS
•
Digital Cross Connect Systems
•
CSU/DSU Equipment
•
Routers
•
Fiber Optic Terminals
•
Multiplexers
•
ATM Switches
F
IGURE
1. XRT73LC03A B
LOCK
D
IAGRAM
E3_(n)
STS-1/DS3_(n)
Host/(HW)
RLOL_(n) EXClk_(n)
RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
REQEN_(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
RxClk_(n)
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
Serial
Processor
Interface
LOS Detector
HDB3/
B3ZS
Decoder
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
Loop MUX
TTIP_(n)
Pulse
Shaping
TRing_(n)
MTIP_(n)
MRing_(n)
DMO_(n)
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Device
Monitor
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
TYPICAL APPLICATIONS
F
IGURE
2. M
ULTI
C
HANNEL
ATM A
PPLICATION
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
REV. 1.0.2
RPOS
RNEG
RxLineClk
RRPOS
RRNEG
RRClk
RTIP
RRing
ATM
Switch/
SAR
XRT74L73
XRT71D03
MClk
XRT73LC03
TPOS
TNEG
TxClk
TPOS
TNEG
TxLineClk
TTIP
TRing
3 Channel E3/DS3 ATM UNI
3 Channel E3/DS3 J/A
3 Channel E3/DS3 LIU
F
IGURE
3. M
ULTI
S
ERVICE
- F
RAME
R
ELAY
A
PPLICATION
RPOS
RNEG
RxLineClk
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
Frame
Relay
XRT72L56
XRT71D03
MClk
XRT73LC03
TPOS
TNEG
TxLineClk
TPOS
TNEG
TxClk
TTIP
TRing
6 Channel E3/DS3 Framer
2 x 3 Channel E3/DS3 J/A
2 x 3 Channel E3/DS3 LIU
TRANSMIT INTERFACE CHARACTERISTICS:
•
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
from the line
•
Integrated Pulse Shaping Circuit
•
Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
•
Contains Transmit Clock Duty Cycle Correction
Circuit on-chip
•
Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
•
Generates pulses that comply with the DSX-3 pulse
template as specified in Bellcore GR-499
-CORE
and ANSI T1.102_1993
•
Generates pulses that comply with the STSX-1
pulse template as specified in Bellcore GR-253-
CORE
•
Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS:
•
Integrated Adaptive Receive Equalization (optional)
and Timing Recovery
•
Declares and Clears the LOS defect per ITU-T
G.775 requirements (E3 and DS3 applications)
•
Meets Jitter Tolerance Requirements as specified
in ITU-T G.823_1993 (E3 Applications)
•
Meets Jitter Tolerance Requirements as specified
in Bellcore GR-499-CORE (DS3 Applications)
•
Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
•
Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
•
Recovered Data can be muted while the LOS Con-
dition is declared
•
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
•
Receiver can be powered down in order to con-
serve power in redundancy designs
2
REV. 1.0.2
EXDG ND
EXDVDD
EXClk_1
REQEN_2
STS1/DS3_2
E3_2
EXClk_2
RxOFF_2
RLOL_1
LCV_1
RLO S_1
RxDGND_1
RPO S_1
RNEG_1
RxClk_1
LOSMUTEN
RxDVDD_1
AGND_1
TxOFF_2
TxOFF_1
TxOFF_0
TxAGND_1
TxAVDD_1
DM O_1
P
ART
#
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
ORDERING INFORMATION
XRT73LC03AIV
P
ACKAGE
F
IGURE
4. P
IN OUT OF THE
XRT73LC03A
IN THE
120 P
IN
LQFP
PACKAGE
120 Pin LQFP 14mm X 20mm
XRT73LC03A
3
O
PERATING TEMPERATURE
R
ANGE
T ND ata_1
TPD ata_1
T xC lk_1
M Ring_1
M TIP_1
TA O S_1
TA O S_2
TxLEV_1
TxLEV_2
TTIP_1
T xAV DD _1
TRing_1
TxAG ND _1
TxAG ND _2
M Ring_2
M TIP_2
TxAG ND _2
TRing_2
T xAV DD _2
TTIP_2
D M O _2
T xAV DD _2
T ND ata_2
TPD ata_2
T xC lk_2
TxAG ND _0
TRing_0
T xAV DD _0
TTIP_0
M TIP_0
M Ring_0
T ND ata_0
TPD ata_0
T xC lk_0
TxLEV_0
TA O S_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
R EG R/(R xC lkINV )
S TS-1/DS 3_1
A G N D_2
S R/(D R )
E 3_1
NC
NC
LO STH R _1
LLB _1
R LB_1
R xA VD D _1
R R ing_1
R TIP_1
R xA G N D_1
R EQ EN _1
R xA G N D_2
R TIP_2
R R ing_2
R xA VD D _2
R LB_2
LLB _2
LO STH R _2
R EQ EN _0
R xA G N D_0
R TIP_0
R R ing_0
R xA VD D _0
R LB_0
LLB _0
LO STH R _0
IC T
S TS-1/DS 3_0
S DO /(E 3_0)
S DI/(R xO FF_0)
S Clk/(R xO FF_1)
C S/(E N DE C DIS )
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
-40
o
C to +85
o
C
XRT73LC03A
R LO L_2
LC V _2
R LO S_2
R LO L_0
LC V _0
R LO S_0
R xD G N D _0
NC
NC
R PO S _0
R N EG _0
R xC lk _0
R xD VD D _0
EX C lk_0
R xD G N D _2
R PO S _2
R N EG _2
R xC lk _2
H O ST/(H W )
R xD VD D _2
AG N D _0
TxA G N D _0
D M O _0
TxA VD D _0
XRT73LC03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
F
EATURES
....................................................................................................................................................
APPLICATIONS .........................................................................................................................................
T
YPICAL
A
PPLICATIONS
.................................................................................................................................
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
: .....................................................................................................
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
: .......................................................................................................
1
1
2
2
2
ORDERING INFORMATION ............................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 7
O
PERATING
M
ODE
S
ELECT
........................................................................................................................... 7
C
ONTROL AND
A
LARM
I
NTERFACE
................................................................................................................. 9
M
ICROPROCESSOR
I
NTERFACE
.................................................................................................................... 11
P
OWER AND
G
ROUND
P
INS
......................................................................................................................... 13
N
O
C
ONNECTION
P
INS
................................................................................................................................ 14
ELECTRICAL CHARACTERISTICS ................................................................................ 15
A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................................................................... 15
SYSTEM DESCRIPTION .................................................................................................. 24
T
HE
T
RANSMIT
S
ECTION
- C
HANNELS
0, 1
AND
2 .........................................................................................
T
HE
R
ECEIVE
S
ECTION
- C
HANNELS
0, 1
AND
2 ...........................................................................................
T
HE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
.................................................................................................
1.0 Selecting the Data Rate ....................................................................................................................
24
24
24
25
1.1 C
ONFIGURING
C
HANNEL
(
N
) ............................................................................................................................... 25
C
OMMAND
R
EGISTER
, CR4-(
N
) ...................................................................................................... 27
2.0 The Transmit Section ....................................................................................................................... 27
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
............................................................................................................................ 27
2.1.1 Accepting Dual-Rail Data from the Terminal Equipment ...................................................................... 27
2.1.2 Accepting Single-Rail Data from the Terminal Equipment ................................................................... 28
C
OMMAND
R
EGISTER
CR1-(
N
) ....................................................................................................... 28
2.2 T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IRCUITRY
...................................................................................
2.3 T
HE
HDB3/B3ZS E
NCODER
B
LOCK
..................................................................................................................
2.3.1 B3ZS Encoding ....................................................................................................................................
2.3.2 HDB3 Encoding ....................................................................................................................................
2.3.3 Disabling the HDB3/B3ZS Encoder .....................................................................................................
29
29
29
30
30
C
OMMAND
R
EGISTER
CR2-(
N
) ....................................................................................................... 30
2.4 T
HE
T
RANSMIT
P
ULSE
S
HAPING
C
IRCUITRY
....................................................................................................... 31
2.4.1 Enabling the Transmit Line Build-Out Circuit ....................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ...................................................................................................... 32
2.4.2 Disabling the Transmit Line Build-Out Circuit ....................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ...................................................................................................... 33
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit ......................................................... 33
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications .................................................................... 33
2.5 I
NTERFACING THE
T
RANSMIT
S
ECTIONS OF THE
XRT73LC03A
TO THE
L
INE
...................................................... 33
T
RANSFORMER
R
ECOMMENDATIONS
............................................................................................... 34
3.0 The Receive Section ......................................................................................................................... 35
3.1 I
NTERFACING THE
R
ECEIVE
S
ECTIONS OF THE
XRT73LC03A
TO THE
L
INE
........................................................ 35
3.2 T
HE
R
ECEIVE
E
QUALIZER
B
LOCK
...................................................................................................................... 36
3.2.1 Guidelines for Setting the Receive Equalizer ...................................................................................... 36
C
OMMAND
R
EGISTER
CR2-(
N
) ....................................................................................................... 37
3.3 C
LOCK
R
ECOVERY
PLL .................................................................................................................................... 38
3.3.1 The Training Mode ............................................................................................................................... 38
3.3.2 The Data/Clock Recovery Mode .......................................................................................................... 38
I
XRT73LC03A
REV. 1.0.2
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
38
38
38
39
3.4 T
HE
HDB3/B3ZS D
ECODER
.............................................................................................................................
3.4.1 B3ZS Decoding (DS3/STS-1 Applications) ..........................................................................................
3.4.2 HDB3 Decoding (E3 Applications) .......................................................................................................
3.4.3 Configuring the HDB3/B3ZS Decoder .................................................................................................
C
OMMAND
R
EGISTER
CR2-(
N
) ...................................................................................................... 39
3.5 LOS D
ECLARATION
/C
LEARANCE
....................................................................................................................... 39
3.5.1 The LOS Declaration/Clearance Criteria for E3 Applications ............................................................... 40
3.5.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications .......................................... 41
C
OMMAND
C
OMMAND
C
OMMAND
C
OMMAND
R
EGISTER
CR0-(
N
)
R
EGISTER
CR2-(
N
)
R
EGISTER
CR0-(
N
)
R
EGISTER
CR2-(
N
)
......................................................................................................
......................................................................................................
......................................................................................................
......................................................................................................
42
42
42
42
3.5.3 Muting the Recovered Data while the LOS is being Declared ............................................................. 42
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 43
3.6 R
OUTING THE
R
ECOVERED
T
IMING AND
D
ATA
I
NFORMATION TO THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
.............. 43
3.6.1 Routing Dual-Rail Format Data to the Receiving Terminal Equipment ................................................ 43
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 45
3.6.2 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment .............. 45
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 45
3.7 S
HUTTING
OFF
THE
R
ECEIVE
S
ECTION
............................................................................................................. 46
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 46
4.0 Diagnostic Features of the XRT73LC03A ...................................................................................... 47
4.1 T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
............................................................................................................ 47
C
OMMAND
R
EGISTER
CR4-(
N
) ...................................................................................................... 48
4.2 T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
. ........................................................................................................... 48
C
OMMAND
R
EGISTER
CR4-(
N
) ...................................................................................................... 48
4.3 T
HE
R
EMOTE
L
OOP
-B
ACK
M
ODE
...................................................................................................................... 49
C
OMMAND
R
EGISTER
CR4-(n) ...................................................................................................... 49
4.4 T
X
OFF F
EATURES
........................................................................................................................................... 50
C
OMMAND
R
EGISTER
CR1-(
N
) ...................................................................................................... 50
4.5 T
HE
T
RANSMIT
D
RIVE
M
ONITOR
F
EATURES
....................................................................................................... 50
4.6 T
HE
TAOS (T
RANSMIT
A
LL
O
NE
S) F
EATURE
.................................................................................................... 51
C
OMMAND
R
EGISTER
CR1-(
N
) ...................................................................................................... 51
5.0 The Microprocessor Serial Interface .............................................................................................. 51
5.1 D
ESCRIPTION OF THE
C
OMMAND
R
EGISTERS
.................................................................................................... 51
5.2 D
ESCRIPTION OF
B
IT
-F
IELDS FOR EACH
C
OMMAND
R
EGISTER
........................................................................... 53
5.2.1 Command Register - CR0-(n) .............................................................................................................. 53
C
OMMAND
R
EGISTER CR
0-(
N
) ....................................................................................................... 53
C
OMMAND
R
EGISTER
CR1-(
N
) ...................................................................................................... 53
5.2.3 Command Register CR2-(n) ................................................................................................................ 54
C
OMMAND
R
EGISTER
CR2-(
N
) ...................................................................................................... 54
C
OMMAND
R
EGISTER
CR3-(
N
) ...................................................................................................... 54
C
OMMAND
R
EGISTER
CR4-(
N
) ...................................................................................................... 55
5.3 O
PERATING THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
. ................................................................................... 56
ORDERING INFORMATION ............................................................................................. 58
PACKAGE DIMENSIONS ................................................................................................. 58
R
EVISION
H
ISTORY
..................................................................................................................................... 59
II
京公网安备 11010802033920号
EEWORLD
