PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
F
EATURES
•
6 LVCMOS / LVTTL outputs
•
Crystal oscillator interface
•
Output frequency range: 10MHz to 50MHz
•
Crystal input frequency range: 10MHz to 50MHz
•
Output skew: 10ps (typical)
•
5V tolerant enable inputs
•
Synchronous output enables
•
Operating supply modes: Full 3.3V, 2.5V and 1.8V,
mixed 3.3Vcore/2.5V or1.8V operating supply, and
mixed 2.5V core/1.8V operating supply
•
-40°C to 85°C ambient operating temperature
•
Pin compatible to MPC905
G
ENERAL
D
ESCRIPTION
The ICS83905I is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83905I single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased from 6 to 12 by utilizing
the ability of the outputs to drive two series terminated lines.
ICS
The ICS83905I is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
mode. Guaranteed output and part-to-part skew characteris-
tics along with the 1.8V output capabilities makes the
ICS83905I ideal for high performance, single ended applica-
tions that also require a limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
BCLK0
XTAL_OUT
ENABLE 2
GND
BCLK0
V
DD
o
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
ENABLE 1
BCLK5
V
DDO
BCLK4
GND
BCLK3
V
DD
BCLK1
XTAL_IN
BCLK2
XTAL_OUT
ICS83905I
BCLK3
BCLK4
ENABLE 1
16-Lead SOIC
3.9mm x 9.9mm x 1.38mm body package
M Pacakge
Top View
SYNCHRONIZE
BCLK5
ICS83905I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm body package
G Pacakge
Top View
XTAL_OUT
ENABLE2
ENABLE1
XTAL_IN
ENABLE 2
SYNCHRONIZE
GND
GND
BCLK0
V
DDO
BCLK1
1
2
20 19 18 17 16
ICS83905I
15
nc
BCLK5
V
DDO
BCLK4
GND
GND
20-Lead VFQFN
14
4mm x 4mm x 0.9mm
3
body package 13
4
K Package
12
5
6
GND
Top View
7
GND
11
BCLK3
8
BCLK2
9 10
V
DD
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83905AMI
http://www.icst.com/products/hiperclocks.html
1
REV. B JUNE 11, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
Type
Description
Cr ystal oscillator interface. XTAL_OUT is the output.
Cr ystal oscillator interface. XTAL_IN is the input.
Output enable. LVCMOS / LVTTL interface levels.
Clock outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Core supply pin.
Output supply pin.
No connect.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Name
XTAL_OUT
XTAL_IN
ENABLE 1, ENABLE2
BCLK0, BCLK1, BCLK2,
BCLK3, BCLK4, BCLK5
GND
V
DD
V
DDO
n/c
Input
Input
Output
Power
Power
Power
Unused
Output
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2V
V
DDO
= 3.3V ± 5%
R
OUT
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
5
7
7
10
Test Conditions
Minimum
Typical
4
19
18
16
12
Maximum
Units
pF
pF
pF
pF
Ω
Ω
Ω
T
ABLE
3. O
UTPUT
E
NABLE
Control Inputs
ENABLE 1
0
0
1
1
AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
Outputs
BCLK0:BCLK4
LOW
LOW
Toggling
Toggling
BCLK5
LOW
Toggling
LOW
Toggling
ENABLE 2
0
1
0
1
83905AMI
http://www.icst.com/products/hiperclocks.html
2
REV. B JUNE 11, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
78.8°C/W (0 mps)
89°C/W (0 lfpm)
38.5°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
16 Lead SOIC package
16 Lead TSSOP package
20 Lead VFQFN package
Storage Temperature, T
STG
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
TBD
TBD
Maximum
3.465
3.465
Units
V
V
µA
µA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
TBD
TBD
Maximum
2.625
2.625
Units
V
V
µA
µA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
1.6
1.6
Typical
1.8
1.8
TBD
TBD
Maximum
2.0
2.0
Units
V
V
µA
µA
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
TBD
TBD
Maximum
3.465
2.625
Units
V
V
µA
µA
83905AMI
http://www.icst.com/products/hiperclocks.html
3
REV. B JUNE 11, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
TBD
TBD
Maximum
3.465
2.0
Units
V
V
µA
µA
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
T
ABLE
4F. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
TBD
TBD
Maximum
2.625
2.0
Units
V
V
µA
µA
T
ABLE
4G. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
Parameter
Input High Voltage
ENABLE1,
ENABLE2
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
IL
Input Low Voltage
ENABLE1,
ENABLE2
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 1.8V ± 0.2V
V
DDO
= 3.3V ± 5%; NOTE 1
V
OH
Output High Voltage
V
DDO
= 2.5V ± 5%; I
OH
= -1mA
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; I
OL
= 1mA
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
Minimum
2
1.7
0.65*V
DD
-0.3
-0.3
-0.3
2.6
2
1.8
V
DD
- 0.3
0.5
0.4
0.45
0.35
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.7
0.35*V
DD
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
83905AMI
http://www.icst.com/products/hiperclocks.html
4
REV. B JUNE 11, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Using External Crystal
Using External Clock Source
HIGH (above 2V); NOTE 1
Minimum Typical Maximum Units
10
DC
0.5T
T = Periods
0.5T
0.5T
0.5T
T = desired Period
TBD
10
20% to 80%
ENABLE 1
ENABLE 2
500
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ms
ms
ms
ms
db
°
50
100
MHz
MHz
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
Output Frequency
t
PW
Output Pulse Width
LOW (below 0.8V), NOTE 2
HIGH (above 2V); NOTE 1
LOW (below 0.8V), NOTE 2
t
PER
Output Period
Output Skew; NOTE 3, 5
Output Rise/Fall Time
Output Enable Time;
NOTE 4
t
sk(o)
t
R
/t
F
t
EN
t
DIS
A
OSC
Phase
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
XTAL_IN to XTAL_OUT Oscillator Gain
Loop Phase Shift Modulo 360°+
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Assuming input duty cycle specs from Recommended Operating Conditons table are met.
NOTE 2: Assuming external crystal or 50% duty cycle external reference is used.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
odc
t
PER
Output Frequency
Output Duty Cycle
Output Period
Output Skew; NOTE 3, 5
Output Rise/Fall Time
Output Enable Time; ENABLE 1
NOTE 4
ENABLE 2
Output Disable Time; ENABLE 1
NOTE 4
ENABLE 2
XTAL_IN to XTAL_OUT Oscillator Gain
Loop Phase Shift Modulo 360°+
20% to 80%
Using External Crystal
Using External Clock Source
Test Conditions
Minimum Typical Maximum Units
10
DC
50
TBD
10
500
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ms
ms
ms
ms
db
°
50
100
MHz
MHz
%
t
sk(o)
t
R
/t
F
t
EN
t
DIS
A
OSC
Phase
See notes from Table 5A.
http://www.icst.com/products/hiperclocks.html
5
83905AMI
REV. B JUNE 11, 2004
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