PC745CMZFU400LE datasheet, PDF

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PC745CMZFU400LE: DescriptionRISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA255, 21 X 21 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, PLASTIC, FCBGA-255; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，60 Pages; Manufacturere2v technologies

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PC745CMZFU400LE Overview

RISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA255, 21 X 21 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, PLASTIC, FCBGA-255

PC745CMZFU400LE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA, BGA255,16X16,50
Contacts	255
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	400 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B255
length	21 mm
low power mode	YES
Number of terminals	255
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA255,16X16,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	2,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	2.8 mm
speed	400 MHz
Maximum supply voltage	2.1 V
Minimum supply voltage	1.9 V
Nominal supply voltage	2 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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PC755/745

PowerPC 755/745 RISC Microprocessor

Datasheet

Features

•

18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755)

15.7SPECint95, 9SPECfp95 at 350 MHz (PC745)

733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

Typical 6.4W at 400 MHz, Full Operating Conditions

Nap, Doze and Sleep Modes for Power Savings

Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch

4 Beta Byte Virtual Memory, 4-GByte of Physical Memory

64-bit Data and 32-bit Address Bus Interface

32-KB Instruction and Data Cache

Six Independent Execution Units

Write-back and Write-through Operations

INT

max = 400 MHz

BUS

max = 100 MHz

Voltage I/O 2.5V/3.3V; Voltage Int 2.0V

Description

The PC755 and PC745 Power Architecture

™

microprocessors are high-performance, low-power, 32-bit implementations of

the Power Architecture Reduced Instruction Set Computer (RISC) architecture, especially enhanced for embedded appli-

cations.

The PC755 and PC745 microprocessors differ only in that the PC755 features an enhanced, dedicated L2 cache interface

with on-chip L2 tags. The PC755 is a drop-in replacement for the award winning Power Architecture 750 microprocessor

and is footprint and user software code compatible with the MPC7400 microprocessor with AltiVec

technology. The

PC745 is a drop-in replacement for the Power Architecture 740 microprocessor and is also footprint and user software code

compatible with the Power Architecture 603e microprocessor. PC755/745 microprocessors provide on-chip debug support

and are fully JTAG-compliant.

The PC745 microprocessor is pin compatible with the TSPC603e family.

Screening

This product is manufactured in full compliance with:

•

HiTCE CBGA According to e2v Standards

CBGA + CI-CGA + FC-PBGA up Screenings Based upon e2v Standards

Full Military Temperature Ranges (T

= -55°C,

= +125°C)

Industrial Temperature Ranges (T

= -40°C, T

+110°C)

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2008

0828J–HIREL–07/08

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