ADVANCE INFORMATION
PE826C32
Product Description
The PE826C32 is a high performance monolithic CMOS
RS-422 line receiver. Its operating supply range is 3.0 to
3.6V, with an input signal common mode range of +/-
10V. The PE826C32 offers higher speed and lower
power than other RS-422 receiver types. It is packaged
in standard DIP and flat pack options and is ideal for
stringent military applications.
The PE826C32 is manufactured in Peregrine’s patented
Ultra Thin Silicon (UTSi®) CMOS process, offering the
performance of GaAs with the low power, economy and
integration of conventional CMOS.
Quad RS-422 Differential Line
Receiver
Features
•
High-speed operation: < 15 nS
typical
•
Low power: < 9 mA typical
•
3.3 V operation
•
Standard packaging: 16-lead
DIP and flat pack
•
Pin Compatible with Existing
Industry Products
Figure 1. Package Drawing
PEREGRINE SEMICONDUCTOR CORP.
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http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 6
PE826C32
Preliminary Specification
Figure 2. Pin Configuration
A-
A+
AQ
E+
BQ
B+
B-
V-
1
2
3
4
5
6
7
8
16
15
14
13
V+
D-
Table 2. Recommended Operating Conditions
Symbol
V+
T
OP
VIN (Line)
D+
DQ
E-
CQ
C+
C-
VIN (Dig)
VOUT
IOUT
V
ESD
Parameter/Conditions
Supply voltage
Operating temperature
range
Maximum input voltage
A+/-, B+/-, C+/-, D+/-
Maximum input voltage
Maximum output voltage
Maximum output current
ESD Voltage Human
Body Model (Note 1)
Min
3.0
-55
-7
0
0
-10
Max
3.6
125
7
(V+)
(V+)
10
1000
Units
V
°C
V
V
V
mA
V
PE26C32
12
11
10
9
Note 1: Periodically sampled, not 100% tested. Tested per MIL-STD-
883 M3015 C2.
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 2.
Latch-Up Avoidance
Description
Channel A Inverting Input
Channel A Noninverting Input
Channel A Output
Enable, active high
Channel B Output
Channel B Noninverting Input
Channel B Inverting Input
Ground Pin
Channel C Inverting Input
Channel C Noninverting Input
Channel C Ouput
Enable, active low
Channel D Output
Channel D Noninverting Input
Channel D Inverting Input
Supply Pin
Table 1. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
A-
A+
AQ
E+
BQ
B+
B-
V-
C-
C+
CQ
E-
DQ
D+
D-
V+
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Device Functional Considerations
The PE826C32 operates at high switching speeds.
In order to obtain maximum performance, it is
crucial that pin 16 be supplied with a bypass
capacitor to ground (pin 8).
Table 3. Truth Table
E+
L
H
X
H
X
H
X
E-
H
X
L
X
L
X
L
Vin (Diff)
X
<-200 mV
>+200 mV
Open
Q
Z
L
H
H
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0146~00A
|
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 6
PE826C32
Advance Information
Table 4. Electrical Specifications
-55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified
Parameter
Supply Voltage
Supply Current (Line inputs open, enabled)
(V+)=3.6V
Input Threshold (Line, differential)
VCM=+7
VCM=0
VCM=-7
Input Threshold Hysteresis (Line, Differential)
VCM=0
Input Resistance (Line pins)
VCM=+7
VCM=0
VCM=-7
Input Current (Line pins)
VCM=+7
VCM=-7
Input Threshold (Enable)
Input Current (Enable)
Input “Failsafe” Open Circuit Differential voltage
Output Drive Current @ 0.5 V from rail (high or low)
Output Short Circuit Current (to V-)
Output Tristate Current, 0 < Vout < V+
VOH @ 10 mA
VOL @ 10 mA
TPHL (See Fig 2)
TPLH (See Fig 2)
TPZL, TPZH (See Fig 3)
TPHZ, TPLZ (See Fig 3)
FMAX
Notes:
Minimum
3.0
Typical
3.3
5
Maximum
3.6
10
200
200
200
Units
V
mA
mV
mV
mV
mV
Ohms
Ohms
Ohms
-200
-200
-200
5
15 K
15 K
15 K
15
100
25 K
25 K
25 K
1000
-1200
(V+)*0.3
-1
200
10
15
-5
(V+) – 0.5 V
0
(V+) – 0.4
0.4
12
12
10
10
50
75
5
(V+)
0.5 V
25
25
25
25
(V+)/2
(V+)*0.7
1
2500
uA
V
uA
mV
mA
mA
uA
V
V
nS
nS
nS
nS
MHz
(1) “Line” pins refer to A-, A+, B-, B+, C-, C+, D-, D+, differential outputs
(2) “Digital Input” or “Enable” pins refer to E+, E-
(3) “Digital Input” pins refer to AQ, BQ, CQ, DQ
(4) Output Short Circuit not intended to imply continuous operation
PEREGRINE SEMICONDUCTOR CORP.
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http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 6
PE826C32
Preliminary Specification
Figure 3. TPLH, TPHL Test Circuit Block Diagram
TPLH, TPHL measured from input 50% to output
50% thresholds. TRISE, TFALL measured from
output 20% to output 80% thresholds.
2,6,10,14
+
VI+
1.0 – 2.0
-
1,7,9,15
VI-
1.0 – 2.0
4,16
DC
8,12
3,5,11,13
CL
15pF
I-
I+
Q
TPLH
TPLH
Figure 2: TPLH, TPHL
Q
TRISE
TFALL
Figure 4. TPLZ, TPZL, TPHZ, TPZH Test Circuit Block Diagram
16
Vcc
3.3V
4
13
VI+
DC
L: 0.0
H: 1.5
2,6,10,14
+
-
E+/E-
0-(V+)
1,7,9,15
DC
DC
TPZH, TPZL measured from input 50% to output
50% thresholds. TPHZ, TPLZ measured from
input 50% to output 10% thresholds.
RL
2KΩ
3,5,11,13
CL
15pF
E-
E+
Q
TPZH
TPHZ
VI-
L: 1.5
H: 0.0
Figure 3: TPHZ, TPZH, TPLZ, TPZL
Q
TPZL
TPLZ
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0146~00A
|
UTSi
CMOS RFIC SOLUTIONS
Page 4 of 6
PE826C32
Advance Information
Table 5. Ordering Information
Order
Code
826C32-01
826C32-11
826C32-21
826C32-00
Part Marking
PE826C32-01
PE826C32-11
PE826C32-21
PE826C32-EK
Description
Engineering Sample
Production Unit, DIP
Production Unit, FP
Evaluation Kit
Package
16-pin DIP
16-pin DIP
16-lead FLAT PACK
Evaluation Board
1/Box
Shipping
Method
25/Tray
25/Tray
1/Box
PEREGRINE SEMICONDUCTOR CORP.
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http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 5 of 6
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