D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
PSoC
®
Programmable System-on-Chip
Features
■
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds up to 24 MHz
❐
Low power at high speed
❐
2.4V to 5.25V Operating Voltage
❐
Operating Voltages Down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC
®
Blocks)
❐
Four Analog Type “E” PSoC Blocks Provide:
• Two Comparators with DAC References
• Single or Dual 10-Bit 28 Channel ADC
❐
4 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐
Complex Peripherals by Combining Blocks
Flexible On-Chip Memory
❐
8K Flash Program Storage 50,000 Erase/Write Cycles
❐
512 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
Complete Development Tools
❐
Free Development Software
(PSoC Designer™)
❐
Full-Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Trace Memory
Precision, Programmable Clocking
❐
Internal ±2.5% 24 and 48 MHz Oscillator
❐
Internal Oscillator for Watchdog and Sleep
Programmable Pin Configurations
❐
25 mA Sink, 10 mA Source on all GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Up to 8 Analog Inputs on GPIO
❐
Configurable Interrupt on All GPIO
Versatile Analog Mux
❐
Common Internal Analog Bus
❐
Simultaneous Connection of I/O Combinations
❐
Capacitive Sensing Application Capability
Additional System Resources
2
❐
I C Master, Slave and Multi-Master to 400 kHz
❐
Watchdog and Sleep Timers
❐
User Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
■
Logic Block Diagram
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 38-12025 Rev. *R
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 10, 2009
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple tradi-
tional MCU-based system components with one low cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and program-
mable interconnect. This architecture enables the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The PSoC architecture, shown in
Figure 1,
consists of four main
areas: the Core, the System Resources, the Digital System, and
the Analog System. Configurable global bus resources allow
combining all the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose I/O (GPIO) are also included.
The GPIO provide access to the global digital and analog inter-
connects.
The Digital System
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user modules. Digital peripheral configurations include the
following.
■
■
■
■
■
■
■
■
■
■
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity
SPI master and slave
I
2
C slave and multi-master
Cyclical Redundancy Checker/Generator (8-bit)
IrDA
Pseudo Random Sequence Generators (8 to 32 bit)
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
System Resources provide the following additional capabilities:
■
■
■
■
■
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in
Table 1
on page 4.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital clocks for increased flexibility.
I
2
C functionality to implement an I
2
C master and slave.
An internal voltage reference, MultiMaster, that provides an
absolute value of 1.3V to a number of PSoC subsystems.
A switch mode pump (SMP) that generates normal operating
voltages off a single battery cell.
Various system resets supported by the M8C.
Digital Clocks
FromCore
To System Bus
ToAnalog
System
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
10 bits of precision.
Row Input
Configuration
The Digital System consists of an array of digital PSoC blocks
that may be configured into any number of digital peripherals.
The digital blocks are connected to the GPIO through a series of
global buses that can route any signal to any pin, freeing designs
from the constraints of a fixed peripheral controller.
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
8
8
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12025 Rev. *R
Page 2 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
The Analog System
The Analog System consists of 4 configurable blocks that allow
the creation of complex analog signal flows. Analog peripherals
are very flexible and may be customized to support specific
application requirements. Some of the common PSoC analog
functions for this device (most available as user modules) are:
■
■
■
■
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins may
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
Pin-to-pin comparator
Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
1.3V reference (as a System Resource)
Track pad, finger sensing.
Chip-wide mux that allows analog input from any I/O pin.
Crosspoint connection between any I/O pin combinations.
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x34 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT Type E block and one SC Type E block. Refer
to the
PSoC Technical Reference Manual
for detailed infor-
mation on the CY8C21x34’s Type E analog blocks.
Figure 2. Analog System Block Diagram
When designing capacitive sensing applications, refer to the
signal-to-noise system level requirement found in Application
Note
AN2403
on
the
Cypress
web
site
at
http://www.cypress.com.
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
■
Array Input
Configuration
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
The I
2
C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
Versatile analog multiplexer system.
■
ACI0[1:0]
A IO
ll
X
X
X
X
ACI1[1:0]
■
ACOL1MUX
Analog MuxBus
■
X
Array
ACE00
ASE10
ACE01
ASE11
■
■
Document Number: 38-12025 Rev. *R
Page 3 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks.
Table 1
lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted in this table.
Table 1. PSoC Device Characteristics
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Digital
I/O
PSoC Part
Number
CY8C29x66
CY8C27x43
CY8C24x94
Flash
Size
32K
16K
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at
www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc.
Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop
and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
up to 4
64
up to 2
44
56
1
16
8
4
4
4
4
0
12
12
48
12
28
8
28
4
4
2
2
0
0
0
4
4
2
2
2
2
0
12
12
6
6
2K
256 16K
Bytes
1K
256 4K
Bytes
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at
www.cypress.com/training.
The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CY8C24x23A up to 1
24
CY8C21x34
CY8C21x23
CY8C20x34
up to 1
28
16
1
4
[1]
512 8K
Bytes
4
[1]
256 4K
Bytes
Cypros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
www.cypress.com/cypros.
up to 0
28
3
[2]
512 8K
Bytes
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming infor-
mation, see the
PSoC Technical Reference Manual
for
CY8C21x34 PSoC devices.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Notes
1. Limited analog functionality
.
2. Two analog blocks and one CapSense.
Document Number: 38-12025 Rev. *R
Page 4 of 46
[+] Feedback
京公网安备 11010802033920号
EEWORLD
