Single-Chip 28 x 1 Gbit/s Layer 2+ Ethernet Switch
Features
■
Benefits
■
Twenty-eight 10/100/1000 Mbits/s Ethernet ports:
— Twenty-four-ports supporting 6-pin SGMII inter-
faces to GbE copper PHYs
— Four SerDes ports
Aggregate 42 Mpackets/s switching capacity (wire
speed operation)
32-bit, 66 MHz
PCI
™ processor interface
One MDIO interface
Integrated packet buffer memory
Integrated address table memories:
— 8192 Layer 2 MAC addresses
Full
IEEE
®
802.1d
®
bridging
Extensive VLAN support:
— Port-based VLANs
— Port-/protocol-based VLANs
— Up to 256 active VLANs
L2/L3/L4 classification for access control list (ACL)
and quality of service (QoS)
Advanced traffic management functions:
—
802.3x
flow control
— Traffic shaping and scheduling
— Traffic policing
— Broadcast/multicast storm control
— Eight queues per port
Link aggregation and mirroring
Advanced 0.13
µm
CMOS technology
525-pin FCBGA package
True switch-on-a-chip technology enables system
vendors to build competitive 28-port gigabit Ether-
net switches
Integrated memories and SerDes for lower system
power and cost
Comprehensive QoS features and wire speed per-
formance supporting enterprise desktop aggrega-
tion switching application
Seamless interface and common API with Agere
TruePHY
™ multiport PHY
■
■
■
■
■
■
■
■
■
■
Target Applications
■
■
Layer 2 gigabit Ethernet desktop switches
28-port gigabit Ethernet switch in stand-alone con-
figuration
High-density gigabit Ethernet fabric switches
■
■
■
Block Diagram
Supervisor_
Access
Packet_Buffer
■
■
■
Packet_Processor
Packet_Processor
Packet_Processor
ACL_
Look-up
Layer_2_
Look-up
1
Statistics_
Accumulator
3
Aggregator/
Distributor
4
Aggregator/
Distributor
1G_
Ethernet_
MAC
0
...
Aggregator/
Distributor
1G_
Ethernet_
MAC
0
78
9
0
...
1G_
Ethernet_
MAC
...
78
9
56
7
Figure 1. Block Diagram
Agere Systems - Proprietary
ET3028-50
Single-Chip 28 x 1 Gbit/s Layer 2+ Ethernet Switch
Preliminary Data Sheet
April 2006
Description
The ET3028-50 is a highly integrated and fully featured Layer 2 Ethernet bridge with integrated MACs, packet buff-
ers, and address tables. The ET3028-50 contains 28
IEEE 802.3z
10/100/1000 Mbits/s Ethernet MACs. Twenty-
four of the MACs connect to external PHYs via 6-pin LVDS SGMII interfaces. The remaining four MACs connect to
external fiber PHYs via SerDes interfaces.
The ET3028-50 features an integrated L2/L3/L4 packet classification engine. The result of each packet classifica-
tion is used to determine the packet’s quality of service treatment and access control. Access to the network by
individual desktops can be controlled by L2 MAC address and TCP/IP layer provisioning. Each port supports up to
eight traffic class queues. Each packet is assigned to a class queue based on its
IEEE 802.1p
coding or IP TOS/
DSCP value. Incoming traffic is policed to ensure the optimum use of network resources. Outgoing traffic is sched-
uled or shaped according to the traffic class and network resource usage.
Integrated address tables and packet buffers enable full bandwidth bridging on all ports at any legitimate frame
length. All internal operations are at wire speed.
A reference system design kit is available for the ET3028-50. For more detailed product and reference design infor-
mation, please contact Agere’s local sales office.
System Diagram
SUPERVISOR CPU
SUBSYSTEM
PCI
ET3028-50
SGMII
SerDes
0
1G PHY
1
24
2
23
1G SFP
25
26
27
1G SFP
1G PHY
Figure 2. System Diagram
2
Agere Systems - Proprietary
Agere Systems Inc.
Preliminary Data Sheet
May 2005
ET3028-50
Single-Chip 28 x 1 Gbit/s Layer 2+ Ethernet Switch
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
System Diagram....................................................................................................................................................... 2
Data Structures ...................................................................................................................................................... 44
Absolute Maximum Ratings ............................................................................................................................. 51
Power Supply Consumption ............................................................................................................................ 52
Registers, Records, and Fields........................................................................................................................ 64
Line Caching.................................................................................................................................................... 64
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