IS61LPS51236A-200B2 datasheet, PDF

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IS61LPS51236A-200B2: DescriptionCache SRAM, 512KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119; Categorystorage storage; File Size246KB，35 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61LPS51236A-200B2 Overview

Cache SRAM, 512KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119

IS61LPS51236A-200B2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.1 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum standby current	0.11 A
Minimum standby current	3.14 V
Maximum slew rate	0.425 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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IS61VPS25672A IS61LPS25672A

IS61VPS51236A IS61LPS51236A

IS61VPS102418A IS61LPS102418A

256K x 72, 512K x 36, 1024K x 18

18Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LPS: V

3.3V + 5%, V

DDQ

3.3V/2.5V + 5%

VPS: V

2.5V + 5%, V

DDQ

2.5V + 5%

• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball

PBGA, and 209-ball (x72) packages

ISSI

FEBRUARY 2004

DESCRIPTION

The

ISSI

IS61LPS/VPS51236A, IS61LPS/VPS102418A,

and IS61LPS/VPS25672A are high-speed, low-power syn-

chronous static RAMs designed to provide burstable, high-

performance memory for communication and networking

applications. The IS61LPS/VPS51236A is organized as

524,288 words by 36 bits, the IS61LPS/VPS102418A is

organized as 1,048,576 words by 18 bits, and the IS61LPS/

VPS25672A is organized as 262,144 words by 72 bits.

Fabricated with

ISSI

's advanced CMOS technology, the

device integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single mono-

lithic circuit. All synchronous inputs pass through regis-

ters controlled by a positive-edge-triggered single clock

input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

250

2.6

250

200

3.1

200

Units

MHz

Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

02/06/04

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