W3H32M72E-667SBI datasheet, PDF

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W3H32M72E-667SBI: DescriptionDDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 18 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208; Categorystorage storage; File Size873KB，31 Pages; ManufacturerWhite Electronic Designs Corporation; Websitehttp://www.wedc.com/

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W3H32M72E-667SBI Overview

DDR DRAM, 32MX72, 0.65ns, CMOS, PBGA208, 18 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208

W3H32M72E-667SBI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	BGA, BGA208,11X19,40
Reach Compliance Code	unknown
access mode	FOUR BANK PAGE BURST
Maximum access time	0.65 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	333 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B208
memory density	2415919104 bit
Memory IC Type	DDR DRAM
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	208
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX72
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA208,11X19,40
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	3.7 mm
self refresh	YES
Maximum standby current	0.035 A
Maximum slew rate	1.7 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
Base Number Matches	1

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White Electronic Designs

W3H32M72E-XSBX

32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

FEATURES



Data rate = 667, 533, 400

Package:

• 208 Plastic Ball Grid Array (PBGA), 18 x 20mm

• 1.0mm pitch



Differential data strobe (DQS, DQS#) per byte

Internal, pipelined, double data rate architecture

4-bit prefetch architecture

DLL for alignment of DQ and DQS transitions with

clock signal

Four internal banks for concurrent operation

(Per DDR2 SDRAM Die)

Programmable Burst lengths: 4 or 8

Auto Refresh and Self Refresh Modes

On Die Termination (ODT)

Adjustable data – output drive strength

Single 1.8V ±0.1V supply



Programmable CAS latency: 3, 4, 5, or 6

Posted CAS additive latency: 0, 1, 2, 3 or 4

Write latency = Read latency - 1* tCK

Commercial, Industrial and Military Temperature

Ranges

Organized as 32M x 72

Weight: W3H32M72E-XSBX - 2.5 grams typical

BENEFITS



65% SPACE SAVINGS vs. FPBGA

Reduced part count

54% I/O reduction vs FPBGA

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Upgradable to 64M x 72 density (contact factory for

information)

* This product is subject to change without notice.

FIGURE 1 – DENSITY COMPARISONS

Actual Size

W3H32M72E-XSBX

11.0

CSP Approach (mm)

11.0

19.0

FBGA

White Electronic Designs

W3H32M72E-XSBX

65%

54%

Area

I/O

Count

5 x 209mm

= 1,045mm

5 x 90 balls = 450 balls

360mm

208 Balls

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

July 2009

Rev. 6

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

TABLE 1 – BALL DESCRIPTIONS

Symbol

ODT

Type

Input

Description

W3H32M72E-XSBX

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When

enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and

UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command.

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing

of the positive edge of CK and negative edge of CK#. Output data (DQS and DQS/DQS#) is referenced to the

crossings of CK and CK#.

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the

DDR2 SDRAM. The speciﬁc circuitry that is enabled/disabled is dependent on the DDR2 SDRAM conﬁguration

and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks

idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down

exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding

CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh.

CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V

is applied during

ﬁ

rst power-up. After

REF

has become stable during the power on and initialization sequence, it must be maintained for proper

operation of the CKE receiver. For proper SELF-REFRESH operation, V

REF

must be maintained.

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands

are masked when CS# is registered HIGH.

Command inputs: RAS#, CAS#, WE# (along with CS#) deﬁne the command being entered.

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled

HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM

loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for

upper byte DQ8–DQ15, of each of U0-U4

Bank address inputs: BA0–BA1 deﬁne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is

being applied. BA0–BA1 deﬁne which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the

LOAD MODE command.

Continued on next page

CK, CK#

Input

CKE

Input

CS#

RAS#, CAS#,

WE#

LDM, UDM

Input

BA0–BA1

Input

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

July 2009

Rev. 6

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
package instruction	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40	BGA, BGA208,11X19,40
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.65 ns	0.65 ns	0.65 ns	0.6 ns	0.65 ns	0.65 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	333 MHz	266 MHz	266 MHz	200 MHz	266 MHz	333 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B208	R-PBGA-B208	R-PBGA-B208	R-PBGA-B208	R-PBGA-B208	R-PBGA-B208
memory density	2415919104 bit	2415919104 bit	2415919104 bit	2415919104 bit	2415919104 bit	2415919104 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	72	72	72	72	72	72
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	208	208	208	208	208	208
word count	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	125 °C	85 °C	125 °C	70 °C	70 °C
Minimum operating temperature	-40 °C	-55 °C	-40 °C	-55 °C	-	-
organize	32MX72	32MX72	32MX72	32MX72	32MX72	32MX72
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA208,11X19,40	BGA208,11X19,40	BGA208,11X19,40	BGA208,11X19,40	BGA208,11X19,40	BGA208,11X19,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	225	225	225	225	225	225
power supply	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192
Maximum seat height	3.7 mm	3.7 mm	3.7 mm	3.7 mm	3.7 mm	3.7 mm
self refresh	YES	YES	YES	YES	YES	YES
Maximum standby current	0.035 A	0.035 A	0.035 A	0.035 A	0.035 A	0.035 A
Maximum slew rate	1.7 mA	1.7 mA	1.7 mA	1.7 mA	1.7 mA	1.7 mA
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	MILITARY	INDUSTRIAL	MILITARY	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30	30
Base Number Matches	1	1	1	1	1	1

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