FD5175TL-32.768K datasheet, PDF

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FD5175TL-32.768K: DescriptionClock Generator, 0.32768MHz, CMOS, CDSO6, 3.20 X 5 MM, CERAMIC LCC-6; CategoryThe embedded processor and controller Microcontrollers and processors; File Size134KB，11 Pages; ManufacturerPletronics; Environmental Compliance

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FD5175TL-32.768K Overview

Clock Generator, 0.32768MHz, CMOS, CDSO6, 3.20 X 5 MM, CERAMIC LCC-6

FD5175TL-32.768K Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	DLCC
package instruction	3.20 X 5 MM, CERAMIC LCC-6
Contacts	6
Reach Compliance Code	unknown
ECCN code	EAR99
JESD-30 code	R-CDSO-N6
JESD-609 code	e4
length	5 mm
Humidity sensitivity level	1
Number of terminals	6
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Maximum output clock frequency	0.32768 MHz
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	LSON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	0.24576 MHz
Certification status	Not Qualified
Maximum seat height	1.35 mm
Maximum supply voltage	1.9 V
Minimum supply voltage	1.7 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	10
width	3.2 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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FD5T Series

FD51xxT-32.768KHz

CMOS Clock Oscillator

January 2008

• Pletronics’ FD51T Series is a quartz crystal

controlled precision square wave generator

• Output frequency 32.768KHz

• Selectable low jitter or spread spectrum output.

• Device characteristics may be either factory or

field programmable

• 1.8V, 2.5 or 3.3V LVCMOS outputs

• 3.2 x 5 mm LCC Ceramic Package

• Stability is much better than an

XY cut

watch crystal.

• Low power

• Tape and Reel or cut tape packaging is

available.

• Designed for high density SMD needs

Vdd 1.8V (5)

Vddout

(6)

Reference

oscillator

optional

Voltage

controlled

Optional

Vcontrol

S2/SCL (1)

S1/SDA (2)

Ground (3)

PLL Multiplier #1

optional

Spread Spectrum

optional

Bypass Mode

MUX #1

Divider #1

/1 to /1023

(4)

Out

- Programming

control

- eePROM

- SDA/SCL

Registers

- Sx Control

Pletronics Inc. certifies this device is in accordance with the

RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.

Pletronics Inc. guarantees the device does not contain the following:

Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s

Weight of the Device: 0.09 grams

Moisture Sensitivity Level: 1 As defined in J-STD-020C

Second Level Interconnect code: e4

Absolute Maximum Ratings:

Parameter

DDOUT

Input Voltage

Output Voltage

Continuous Output Current

Unit

-0.5V to +2.5V

-0.5V to +4.6V

-0.5V to V

+ 0.5V

-0.5V to V

DDOUT

+ 0.5V

_ 50 mA

125

C/Watt

Tj Maximum Junction Temperature

Thermal Resistance, Junction to Case

Product information is current as of publication date. The product conforms

to specifications per the terms of the Pletronics standard warranty. Production

processsing does not necessarily include testing of all parameters.

FD51xxT-32.768KHz

CMOS Clock Oscillator

January 2009

Description:

The FD51xxT-32.768K is derived from the PLE FD51T series Programmable CMOS Clock Oscillator

which is a modular PLL-based low cost, high-performance oscillator. The frequency output is set to

32.768KHz. The FD51xxT-32.768K base frequency is a 24.576MHz AT cut fundamental mode crystal.

The FD5T has a separate output supply pin, V

DDOUT

, for either 1.8, 2.5 or 3.3V output logic levels. The

device supply, V

which provides power to all the internal circuits, is nominally 1.8V.

The PLL is only utilized to support Spread Spectrum Clocking (SSC), in all other cases the PLL is disabled

to reduce power. SSC may be programmed to be either center-spread or down-spread. This is an

important technique to reduce electro-magnetic interference (EMI).

The device supports non-volatile eePROM programming for easy customization of the device. As

shipped, the device is pre-programmed. However, the FD51xxT-32.768K may be reprogrammed to a

different configuration. Reprogramming may be either prior to assembly, or in-circuit via a 2-wire

SDA/SCL I

C bus. In-circuit programming is not allowed if the VCXO function is needed.

Two programmable control inputs, S1 and S2, may be used to control various aspects of

FD51xxT-32.768K operation including selection of alternative frequency set(s), selection of SSC

functionality, output tri-state and power-down.

Reference Oscillator

The VCXO input has a limited voltage range, the VCXO is associated with the internal 1.8V core. A

resistor in series with the Vcontrol input will permit interfacing to 3.3V analog circuits, the voltage range

that changes the frequency will still be limited but the larger voltages swings will not cause problems.

The VCXO function is only enabled (internally connected) if the part number indicates a VCXO

specification. When the VCXO function is enabled the I

C programming mode will be disabled.

PLL Multiplier

The PLL Multiplier is enabled when tight tolerances are needed or when the spread spectrum function is

needed.

Spread Spectrum

The PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the

modulation of the output frequency by a user-set amount.

Divider Section

The dividers operate on the output of the PLL. The divider on the PLL can divide by 1 through 1023 and

is set to 750 in this case. There is only 1 setting allowed per divider. These are not set by the Sx input

state.

The dividers add very little jitter to the output signals.

Multiplexers

MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from

www.pletronics.com

425-776-1880

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