A82DL16x2T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,
A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only,
Simultaneous Operation Flash Memory and 2M (128Kx16 Bit) Static RAM
Preliminary
Document Title
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit
(2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 2M
(128Kx16 Bit) Static RAM
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Update Figure 23
Issue Date
March 25, 2005
May 17, 2005
Remark
Preliminary
PRELIMINARY (May, 2005, Version 0.1)
AMIC Technology, Corp.
A82DL16x2T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,
A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only,
Simultaneous Operation Flash Memory and 2M (128Kx16 Bit) Static RAM
Preliminary
DISTINCTIVE CHARACTERISTICS
MCP Features
Single power supply operation 2.7 to 3.6 volt
High Performance
- Access time as fast as 70ns
Package 69-Ball TFBGA (8x11x1.4 mm)
Industrial operating temperature range: -40°C to 85°C
for –U; -25°C to 85°C for –I
-
Suspends erase operations to allow programming in
same bank
Data
Polling and Toggle Bit
-
Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
-
Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/
Busy
output (RY/
BY
)
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin (
RESET
)
- Hardware method of resetting the internal state machine
to reading array data
WP
/ACC input pin
- Write protect (
WP
) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function accelerates program timing
Sector protection
- Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program
or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
Flash Features
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package
-
69-Ball TFBGA (8x11x1.4 mm)
Top or bottom boot block
Manufactured on 0.18 µm process technology
- Compatible with AM42DL16x2D devices
Compatible with JEDEC standards
-
Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
-
Access time as fast as 70ns
-
Program time: 7µs/word typical utilizing Accelerate
function
Ultra low power consumption (typical values)
-
2mA active read current at 1MHz
-
10mA active read current at 5MHz
-
200nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125°C
-
Reliable operation for the life of the system
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
LP SRAM Features
Power supply range: 2.7V to 3.6V
Access times: 70 ns (max.)
Current:
Very low power version: Operating: 35mA(max.)
Standby: 10uA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chips enable inputs for easy
application
Data retention voltage: 2.0V (min.)
PRELIMINARY (May, 2005, Version 0.1)
1
AMIC Technology, Corp.
A82DL16x2T(U) Series
GENERAL DESCRIPTION
The A82DL16x2T(U) family consists of 16 megabit, 3.0 volt-
only flash memory devices, organized as 1,048,576 words of
16 bits each or 2,097,152 bytes of 8 bits each. Word mode
data appears on I/O
0
–I/O
15
; byte mode data appears on I/O
0
–
I/O
7
. The device is designed to be programmed in-system
with the standard 3.0 volt VCC supply, and can also be
programmed in standard EPROM programmers.
The device is available with an access time of 70ns. The
devices are offered in 69-ball Fine-pitch BGA. Standard
control pins—chip enable (
CE_F
), write enable (
WE
), and
output enable (
OE
)—control normal read and write
operations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power supply
for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
A82DL16x2T(U) Features
The device offers complete compatibility with the
JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device
status bits:
RY/
BY
pin, I/O
7
(
Data
Polling) and I/O
6
/I/O
2
(toggle bits).
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The
hardware sector protection
feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the
automatic sleep mode.
The system
can also place the device into the
standby mode.
Power
consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A82DL16x2T(U) devices uses multiple bank archi-
tectures to provide flexibility for different applications. Three
devices are available with these bank sizes:
Device
DL1622
DL1632
DL1642
Bank 1
2 Mb
4 Mb
8 Mb
Bank 2
14 Mb
12 Mb
8 Mb
PRELIMINARY
(May, 2005, Version 0.1)
2
AMIC Technology, Corp.
A82DL16x2T(U) Series
Pin Configurations
69-Ball TFBGA
Top View
Flash only
A1
A5
A6
A10
NC
B1
B3
B4
NC
B5
NC
B6
B7
B8
NC
SRAM only
Shared
NC
C2
A7
C3
LB_S
C4
WP/ACC
C5
WE
C6
A8
C7
A11
C8
C9
A3
D2
A6
D4
UB_S
D4
RESET
D5
CE2_S
D6
A19
D7
A12
D8
A15
D9
A2
E1
E2
A5
E3
A18
E4
RY/BY
NC
A9
E7
A13
E8
NC
E9
E10
NC
F1
A1
F2
A4
F3
A17
F4
A10
F7
A14
F8
NC
F9
NC
F10
NC
A0
G2
VSS
G3
I/O1
G4
G5
G6
I/O6
G7
NC
G8
A16
G9
NC
CE_F
H2
OE
H3
I/O9
H4
I/O3
H5
I/O4
H6
I/O13
H7
I/O15(A-1) BYTE_F
H8
H9
CE1_S
I/O0
J3
I/O10
J4
VCC_F
J5
VCC_S
J6
I/O12
J7
I/O7
J8
VSS
I/O8
K1
I/O2
I/O11
K5
NC
K6
I/O5
I/O14
K10
NC
NC
NC
NC
Special Handling Instructions for TFBGA Package
Special handling is required for Flash Memory products in TFBGA packages.
Flash memory devices in TFBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or
data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time
PRELIMINARY
(May, 2005, Version 0.1)
3
AMIC Technology, Corp.
A82DL16x2T(U) Series
Product Information Guide
Part Number
Speed Options
Max Access Time (ns)
CE_F
/
CE_S
Access (ns)
Standard Voltage Range:
VCC_F/VCC_S=2.7-3.6V
A82DL16x2T(U)
70
70
70
40
OE
Access (ns)
MCP Block Diagram
VCC_F
A19 to A0
A19 to A0
BYTE_F
WP/ACC
CE_F
RESET
VSS
RY/BY
16M Bit
Flash Memory
I/O
15
(A-1) to I/O
0
I/O
15
(A-1) to I/O
0
VCC_S
VSS
A16 to A0
WE
OE
LB_S
UB_S
CE1_S
CE2_S
2M Bit
Static RAM
I/O
15
(A-1) to I/O
0
PRELIMINARY
(May, 2005, Version 0.1)
4
AMIC Technology, Corp.
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