M16C/6S Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0014-0501
Rev.5.01
Dec 10, 2009
Overview
The M16C/6S group are highly integrated single-chip microcomputers with PLC (Power Line Communica-
tion) modem core and AFE (Analog Front End) in a 64-pin plastic molded LQFP package, which incorpo-
rates IT800 PLC modem technology developed by Yitran Communications Ltd. M16C/60 Series CPU core
enables a high level of code efficiency and high-speed operation. In addition, the implementation of Yitran's
patented DCSK (Differential Code Shift Keying) spread spectrum modulation technique in the IT800 mo-
dem core enables extremely robust communication over the existing electrical wiring, with data rates up to
7.5Kbps. The M16C/6S complies with worldwide regulations (FCC part 15, ARIB and CENELEC bands)
and is suitable for a variety of narrowband applications like smart metering and home networking.
Applications
Power Line Communication
------Table of Contents------
Overview ......................................................... 1
Memory ......................................................... 10
Central Processing Unit (CPU) ..................... 11
SFR ............................................................... 13
Reset ............................................................. 19
Processor Mode ............................................ 23
Clock Generation Circuit ............................... 27
Protection ...................................................... 46
Interrupts ....................................................... 47
Watchdog Timer ............................................ 66
DMAC ........................................................... 68
Timers ........................................................... 78
Timer A ...................................................... 79
Serial I/O ....................................................... 92
Clock Synchronous serial I/O Mode ........ 101
UART Mode ............................................. 109
Special Mode ........................................... 117
SI/O3 and SI/O4 ...................................... 132
Programmable I/O Ports ............................. 137
Electrical Characteristics ............................. 149
Flash Memory Version ................................ 160
IT800AFE (Analog Front End) .................... 184
Usage Notes ............................................... 189
Appendix ..................................................... 199
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.5.01 Dec 10, 2009
REJ03B0014-0501
page 1 of 201
M16C/6S Group
Overview
Performance Outline
Table 1.1.1 lists performance outline of M16C/6S group.
Table 1.1.1. Performance outline of M16C/6S group
CPU
Item
Number of basic instructions
Minimum Instruction Execution
time
Operation Mode
Memory Space
Memory Capacity ROM
RAM
Port
Multifunction Timer
Serial I/O
Performance
91 instructions
65.1 ns (f(BCLK)= 15.36MH
Z
, V
CC
= 3.0V to 3.6V)
Single-chip mode
1M Byte
See Tables 1.1.3 and 1.1.4 Product List
24K Byte
Peripheral
Input/Output : 21 pins, Input : 1 pin
Function
Timer A : 16 bits x 5 channels,
2 channels
Clock synchronous, UART, I
2
C bus
(1)
,
1 channel
UART, I
2
C bus
(1)
,
2 channels
Clock synchronous(*)
(*) 1 channel is internally connected to IT800
DMAC
2 channels
Watchdog Timer
15 bits x 1 channel (with prescaler)
Interrupt
21 internal and 3 external sources, 4 software sources, 7 levels
Clock Generation Circuit
2 circuits
Main clock generation circuit with PLL synthesizer (*),
On-chip oscillator,
(*) This circuit contains a built-in feedback resister.
Electrical
Power supply voltage
3.0V to 3.6V
Characteristics Power Consumption
70mA (V
CC
= V
CC
A= 3.3V, f(X
IN
)= 5.12MHz)
Flash memory Program/Erase Supply Voltage 3.0V to 3.6V (Topr= 0 to 60°C)
Version
Program and Erase Endurance 100 times or 1,000 times
(2)
Power consumption
70mA (V
CC
= V
CC
A= 3.3V, f(X
IN
)= 5.12MHz)
Operating Ambient Temperature
(2)
-20 to 85°C
-40 to 85°C
-40 to 105°C
Package
64-pin plastic mold LQFP
Notes:
1. I
2
C Bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. See Tables 1.1.5 and 1.1.6 Product code for increased program/erase cycle version, and version of
expanded operating ambient temperature.
Rev.5.01 Dec 10, 2009
REJ03B0014-0501
page 2 of 201
M16C/6S Group
Overview
IT800 PHY performance outline of M16C/6S group.
The IT800 PHY is a PLC optimized Physical Layer (PHY) which consists of IT800 modem core and internal
AFE (Analog Front End). The implementation of Yitran's patented DCSK spread spectrum modulation
technique in the IT800 modem core enables extremely robust communication over the existing electrical
wiring, with data rates up to 7.5Kbps. In addition to the inherent interference immunity provided by the
DCSK modulation, the IT800 PHY utilizes several mechanisms for enhanced communication robustness,
such as forward short block soft decoding error correction algorithm and special synchronization algo-
rithms.
The IT800PHY communicates M16C core with clock synchronous serial I/O, interrupt and input/output
ports in M16C/6S (Note). M16C/6S requires external AFE. Table 1.1.2 lists IT800 PHY performance outline
of M16C/6S group.
Table 1.1.2. IT800 PHY performance outline of M16C/6S group
Item
Features
Performance
High immunity to signal fading, various noise characteristics,
impedance modulation and phase/frequency distortion
High in-phase and cross-phase reliability
DCSK (Differential Code Shift Keying)*
*Yitran patented modulation technique
Forward short-block soft decoding error correction mechanism,
CRC-16
FCC, ARIB, EN50065-1-CENELEC
120-400 KHz
7.5Kbps Standard Mode (SM)
5.0Kbps Robust Mode (RM)
1.25Kbps Extremely Robust Mode (ERM)
A-Band (Outdoor): 20-80 KHz
B-Band (Indoor): 95-125 KHz
2.5 Kbps Robust Mode (RM)
0.625Kbps Extremely Robust Mode (ERM)
10bit-D/A converter, preamp,
1bit-A/D converter x 3 channels
Modulation Technique
Error Correction/Detection
Complies with W/W Regulations
Data Rate &
FCC & ARIB
Frequency Band
CENELEC
Internal AFE
Note:
Direct operation of IT800 PHY is not recommended. Since the Layer 2 (DLL) handles the channel access
procedure, using the IT800DLL as such assures coexistence with other IT800 technology based products,
regardless of the vendor, protocol and the application. There is NO such coexistence if the device is used
in direct operation of IT800 PHY. Note that the coexistence here is not with other technologies but with
other IT800 technology based products. As for details, please refer to the next section and Appendix.
About Firmware
Renesas recommends IT800DLL (Product name: D2DL) as a Data Link Layer (DLL) of M16C/6S group.
The IT800 DLL is a PLC optimized DLL especially for the products based on Yitran's IT800 technology. For
availability of IT800DLL, please contact Renesas technical support representative. For more details about
the IT800DLL advantages, please refer to Appendix.
Rev.5.01 Dec 10, 2009
REJ03B0014-0501
page 3 of 201
Block Diagram of Chip
M16C/6S Group
M16C Core
P11
TEST_A
TS
P41
IT800 Modem
Core
Internal AFE
Line
driver
M16C/60 series 16-bit CPU core
register
R2
R3
A1
TS
10
SO
P10
TEST_C
IOUTC
Buffer
10bit D/A
Re
xt
IOUT
Buffer
1
Port P1
8
Port P6
5
Port P7
5
Port P8
Port P8
5
3
Port P9
Rev.5.01 Dec 10, 2009
REJ03B0014-0501
Line
coupling
Preamplifier
PRE_INP
PRE_INN
VREF
P95/CLK4
P96/SOUT4
P97/SIN4
P40
TXnRX
CLR
nPHY_RES
nCD1
1bit-A/D x 3
nCD0
nINT
OPAMP
R0H
R1H
R0L
R1L
Program Counter
A0
FB
SB
PC
Vector table
Stac P
k ointer
INTB
USP
ISP
Multiplier
Flag register
Block Diagram and PLC application Outline
Figure 1.1.1. Block Diagram of Chip and PLC application Outline
Inner
Ports
DCLK
DI
DO
BUFFER
OPAMP
Figure 1.1.1 is a block diagram of the M16C/6S group and PLC application Outline.
page 4 of 201
PRE_BOUT
P42
P56
P54
P53
P82/INT0
SI1
Compar
ator
FLG
Internal Peripherals
Clock synchronous serial I/O
(8bits
✕
2channels)
UART or
Clock synchronous serial I/O
(8bits
✕
3channels)
VccA
VssA
CH1_INP
AMP1_OUT
AMP1_IN
Watchdog timer
(15bits)
Filters
Timer (16bits)
Output (TimerA) 5
BPF
100 to 200KHz
CH1_INN
FB1
CH2_INP
AMP2_OUT
AMP2_IN
DMA C
(2channels)
EXTCLK 15.36MHz
System clock generator
Memory
OPAMP
BPF
VREF
CH2_INN
FB2
CH3_INP
AMP3_OUT
AMP3_IN
OPAMP
ROM
RAM
SI2
Compar
ator
200 to 300KHz
XIN
SI3
CLK_IN 46.08MHz
BPF
Compar
ator
5.12MHz
PLL module
300 to 400KHz
CH3_INN
FB3
XOUT
Overview
M16C/6S Group
Overview
Product List
Tables 1.1.3 and 1.1.4 list the M16C/6S group product and Figure 1.1.2 shows the type numbers, memory
sizes and packages.
Table 1.1.3. Product List (1) M16C/6S
Type No.
M306S0FAGP
(D): under development
ROM capacity
96K bytes
RAM capacity
24K bytes
Package type
PLQP0064KB-A (64P6Q-A)
Remarks
Flash memory
Current of Dec. 2009
Product Code
U3, U5, U7(D), U9(D)
Table 1.1.4. Product List (2) M16C/6S D-version
Type No.
M306S0F8DGP
M306S0FADGP
ROM capacity
64K bytes
96K bytes
RAM capacity
24K bytes
24K bytes
Package type
PLQP0064KB-A (64P6Q-A)
PLQP0064KB-A (64P6Q-A)
Remarks
Current of Dec. 2009
Product Code
Flash memory U3
Flash memory U3
Type No.
M 3 0 6 S 0 F A D G P – U3
Product code
See Tables 1.1.5 and 1.1.6 Product code
Package type:
GP : Package
64P6Q-A
Version
(no) : M16C/6S
D : M16C/6S D-version
ROM capacity:
8: 64K bytes
A: 96K bytes
Memory type:
F: Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/6S Group
M16C Family
Figure 1.1.2. Type No., Memory Size, and Package
Rev.5.01 Dec 10, 2009
REJ03B0014-0501
page 5 of 201
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