M32C/84 Group (M32C/84, M32C/84T)
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0047-0121
Rev.1.21
Jul. 08, 2005
1. Overview
The M32C/84 group (M32C/84, M32C/84T) microcomputer is a single-chip control unit that utilizes high-
performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/84 group
(M32C/84, M32C/84T) is available in 144-pin and 100-pin plastic molded LQFP/QFP packages.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili-
ties to process complex instructions by less bytes and execute instructions at higher speed.
It includes a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments, and other high-speed processing applications.
1.1 Applications
Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev. 1.21 Jul. 08, 2005
Page 1 of 85
M32C/84 Group (M32C/84, M32C/84T)
1. Overview
1.2 Performance Overview
Tables 1.1 and 1.2 list performance overview of the M32C/84 group (M32C/84, M32C/84T).
Table 1.1 M32C/84 Group (M32C/84, M32C/84T) Performance (144-Pin Package)
Characteristic
Performance
M32C/84
M32C/84T
CPU
Basic Instructions
108 instructions
Shortest Instruction Execution Time 31.3 ns
31.3 ns
(f(BCLK)=32 MHz, V
CC1
=4.2 V to 5.5 V) (f(BCLK)=32 MHz, V
CC1
=4.2 V to 5.5 V)
41.7 ns
(f(BCLK)=24 MHz, V
CC1
=3.0 V to 5.5 V)
Operation Mode
Single-chip mode, Memory expansion Single-chip mode
mode and Microprocessor mode
Address Space
16 Mbytes
Memory Capacity
See Table 1.3
Peripheral I/O Port
123 I/O pins and 1 input pin
Function Multifunction Timer
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Intelligent I/O
Time measurement function or Waveform generating function:
16 bits x 8 channels
Communication function (Clock synchronous serial I/O, Clock asyn-
chronous serial I/O, HDLC data processing)
Serial I/O
5 Channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus
(1)
, I
2
C bus
(2)
CAN Module
1 channel Supporting CAN 2.0B specification
A/D Converter
10-bit A/D converter: 1 circuit, 34 channels
D/A Converter
8 bits x 2 channels
DMAC
4 channels
DMAC II
Can be activated by all peripheral function interrupt sources
Immediate transfer, Calculation transfer and Chain transfer functions
CRC Calculation Circuit
CRC-CCITT
X/Y Converter
16 bits x 16 bits
Watchdog Timer
15 bits x 1 channel (with prescaler)
Interrupt
38 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
Clock Generation Circuit
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip
oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator or
crystal oscillator must be connected externally
Oscillation Stop Detect Function
Main clock oscillation stop detect function
Voltage Detection Circuit
Available (optional)
Not available
(4)
Electrical Supply Voltage
V
CC1
=4.2 V to 5.5 V, V
CC2
=3.0 V to V
CC1
V
CC1
=V
CC2
=4.2 V to 5.5 V,
Charact-
(f(BCLK)=32 MHz)
(f(BCLK)=32 MHz)
(3)
eristics
V
CC1
=3.0 V to 5.5 V, V
CC2
=3.0 V to V
CC1
(f(BCLK)=24 MHz)
Power Consumption
28 mA (V
CC1
=V
CC2
=5 V,
28 mA (V
CC1
=V
CC2
=5 V,
f(BCLK)=32 MHz)
f(BCLK)=32 MHz)
10µA (V
CC1
=V
CC2
=5 V,
22 mA (V
CC1
=V
CC2
=3.3 V,
f(BCLK)=24 MHz)
f(BCLK)=32 kHz, in wait mode)
10µA (V
CC1
=V
CC2
=5 V,
f(BCLK)=32 kHz, in wait mode)
Flash
Program/Erase Supply Voltage
3.3 V
±
0.3 V or 5.0 V
±
0.5 V
5.0 V
±
0.5 V
Memory Program and Erase Endurance
100 times (all space)
–40 to 85
o
C (T version)
Operating Ambient Temperature
–20 to 85
o
C
–40 to 85
o
C (optional)
Package
144-pin plastic molded LQFP
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
3. The supply voltage of M32C/84T (High-reliability version) must be V
CC1
=V
CC2
.
4. The cold start-up/warm start-up determine function is available only at the user's option.
All options are on a request basis.
Rev. 1.21 Jul. 08, 2005
Page 2 of 85
M32C/84 Group (M32C/84, M32C/84T)
1. Overview
Table 1.2 M32C/84 Group (M32C/84, M32C/84T) Performance (100-Pin Package)
Characteristic
Performance
M32C/84
M32C/84T
CPU
Basic Instructions
108 instructions
Shortest Instruction Execution Time 31.3 ns
31.3 ns
(f(BCLK)=32 MHz, V
CC1
=4.2 V to 5.5 V) (f(BCLK)=32 MHz, V
CC1
=4.2 V to 5.5 V)
41.7 ns
(f(BCLK)=24 MHz, V
CC1
=3.0 V to 5.5 V)
Operation Mode
Single-chip mode, Memory expansion Single-chip mode
mode and Microprocessor mode
Address Space
16 Mbytes
Memory Capacity
See Table 1.3
Peripheral I/O Port
87 I/O pins and 1 input pin
Function Multifunction Timer
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Intelligent I/O
Time measurement function or Waveform generating function:
16 bits x 8 channels
Communication function (Clock synchronous serial I/O, Clock asyn-
chronous serial I/O, HDLC data processing)
Serial I/O
5 Channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus
(1)
, I
2
C bus
(2)
CAN Module
1 channel Supporting CAN 2.0B specification
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
4 channels
DMAC II
Can be activated by all peripheral function interrupt sources
Immediate transfer, Calculation transfer and Chain transfer functions
CRC Calculation Circuit
CRC-CCITT
X/Y Converter
16 bits x 16 bits
Watchdog Timer
15 bits x 1 channel (with prescaler)
Interrupt
38 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
Clock Generation Circuit
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip
oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator or
crystal oscillator must be connected externally
Oscillation Stop Detect Function
Main clock oscillation stop detect function
Voltage Detection Circuit
Available (optional)
Not available
(4)
Electrical Supply Voltage
V
CC1
=4.2 V to 5.5 V, V
CC2
=3.0 V to V
CC1
V
CC1
=V
CC2
=4.2 V to 5.5 V,
Charact-
(f(BCLK)=32 MHz)
(f(BCLK)=32 MHz)
(3)
eristics
V
CC1
=3.0 V to 5.5 V, V
CC2
=3.0 V to V
CC1
(f(BCLK)=24 MHz)
28 mA (V
CC1
=V
CC2
=5 V,
Power Consumption
28 mA (V
CC1
=V
CC2
=5 V,
f(BCLK)=32 MHz)
f(BCLK)=32 MHz)
22 mA (V
CC1
=V
CC2
=3.3 V,
10µA (V
CC1
=V
CC2
=5 V,
f(BCLK)=24 MHz)
f(BCLK)=32 kHz, in wait mode)
10µA (V
CC1
=V
CC2
=5 V,
f(BCLK)=32 kHz, in wait mode)
Flash
Program/Erase Supply Voltage
3.3 V
±
0.3 V or 5.0 V
±
0.5 V
5.0 V
±
0.5 V
Memory Program and Erase Endurance
100 times (all space)
Operating Ambient Temperature
–20 to 85
o
C
–40 to 85
o
C (T version)
–40 to 85
o
C (optional)
Package
100-pin plastic molded LQFP/QFP
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
3. The supply voltage of M32C/84T (High-reliability version) must be V
CC1
=V
CC2
.
4. The cold start-up/warm start-up determine function is available only at the user's option.
All options are on a request basis.
Rev. 1.21 Jul. 08, 2005
Page 3 of 85
M32C/84 Group (M32C/84, M32C/84T)
1. Overview
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/84 group (M32C/84, M32C/84T) microcomputer.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
(3)
V
CC2
Port P4
Port P5
Port P6
<
Peripheral Functions
Timer (16 bits)
Timer A: 5 channels
Timer B: 6 channels
Three-Phase Motor Control Circuit
Watchdog Timer (15 bits)
D/A Converter:
8 bits x 2 channels
>
<
V
CC1(3)
>
Clock Generation Circuit
X
IN
- X
OUT
X
CIN
- X
COUT
On-chip Oscillator
PLL Frequency Synthesizer
A/D Converter:
1 circuit
Standard: 10 inputs
Maximum: 34 inputs
(2)
UART/Clock Synchronous Serial I/O:
5 channels
X/Y Converter:
16 bits x 16 bits
CAN Module: 1 channel
Port P7
8
DMAC
Port P8
DMACII
CRC Calculation Circuit (CCITT):
X
16
+X
12
+X
5
+1
7
<
V
CC1(3)
>
P8
5
M32C/80 series CPU Core
Intelligent I/O
Time Measurement: 8 channels
Waveform Generating: 8 channels
Communication Functions:
Clock Synchronous Serial I/O, UART,
HDLC Data Processing
R0H
R1H
R2
R3
A0
A1
FB
SB
R0L
R1L
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Memory
ROM
Port P9
8
RAM
Port P10
8
Multiplier
<
V
CC1(3)
>
Port P14
Port P15
Port P11
<
V
CC2(3)
>
Port P12
Port P13
7
8
5
8
8
(Note 1)
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. Included in the 144-pin package only.
3. The supply voltage of M32C/84T (High-reliability version) must be V
CC1
=V
CC2
.
Figure 1.1 M32C/84 Group (M32C/84, M32C/84T) Block Diagram
Rev. 1.21 Jul. 08, 2005
Page 4 of 85
M32C/84 Group (M32C/84, M32C/84T)
1. Overview
1.4 Product Information
Table 1.3 lists product information. Figure 1.2 shows the product numbering system.
Table 1.3 M32C/84 Group (1) (M32C/84)
Type Number
M30845FJGP
M30843FJGP
M30843FJFP
M30845FHGP
M30843FHGP
M30843FHFP
M30845FWGP
M30843FWGP
M30845MW-XXXGP
M30843MW-XXXGP
M30843MW-XXXFP
M30842ME-XXXGP
M30840ME-XXXGP
M30840ME-XXXFP
M30842MC-XXXGP
M30840MC-XXXGP
M30840MC-XXXFP
M30842SGP
M30840SGP
M30840SFP
(D): Under Development
(D)
(D)
(D)
Package
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
PLQP0144KA-A (144P6Q-A)
Flash Memory
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
PLQP0144KA-A (144P6Q-A)
320K+4K
PLQP0100KB-A (100P6Q-A)
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
10K
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
---
ROMless
128K
192K
16K
Mask ROM
320K
384K+4K
24K
512K+4K
ROM
Capacity
RAM
Capacity
As of July, 2005
Remarks
Table 1.3 M32C/84 Group (2) (T Version, M32C/84T)
Type Number
M30845FJTGP
M30843FJTGP
M30845FHTGP
M30843FHTGP
M30843FWTGP
M30842MCT-XXXGP
M30840MCT-XXXGP
(D): Under Development
(D)
(D)
Package
PLQP0144KA-A (144P6Q-A)
512K+4K
PLQP0100KB-A (100P6Q-A)
PLQP0144KA-A (144P6Q-A)
384K+4K
PLQP0100KB-A (100P6Q-A)
PLQP0100KB-A (100P6Q-A)
PLQP0144KA-A (144P6Q-A)
128K
PLQP0100KB-A (100P6Q-A)
10K
320K+4K
24K
ROM
Capacity
RAM
Capacity
As of July, 2005
Remarks
Flash Memory
T Version
(High-releability
85° C Version)
Mask ROM
Rev. 1.21 Jul. 08, 2005
Page 5 of 85
京公网安备 11010802033920号
EEWORLD
