MOSEL VITELIC
V62C3184096
512K X 8, CMOS STATIC RAM
PRELIMINARY
Features
s
s
s
s
s
s
s
s
High-speed: 55, 70 ns
Ultra low standby current of 5
µ
A (max.)
Fully static operation
All inputs and outputs directly compatible
Three state outputs
Ultra low data retention current (V
CC
= 2.0V)
Operating voltage: 2.7V–3.3V
Packages
– 32-Pin TSOP (Standard)
– 36-Ball CSP BGA (8mm x 10mm)
Description
The V62C3184096 is a very low power CMOS
static RAM organized as 524,288 words by 8 bits.
Easy memory expansion is provided by an active
LOW CE1, and active HIGH CE2, an active LOW
OE, and three static I/O’s. This device has an
automatic power-down mode feature when
deselected.
Functional Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
Input Buffer
Row Decoder
Sense Amp
I/O
8
1024
x
4096
I/O1
Column Decoder
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
Control
Circuit
OE
WE
CE1
CE2
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
–40
°
C to +85
°
C
Package Outline
T
•
•
B
•
•
Access Time (ns)
55
•
•
70
•
•
L
•
Power
LL
•
•
Temperature
Mark
Blank
I
V62C3184096 Rev. 1.1 June 2000
1
MOSEL VITELIC
Pin Descriptions
A
0
–A
18
Address Inputs
These 19 address inputs select one of the 512K x 8
bit segments in the RAM.
CE
1
, CE
2
* Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
Output Enable Input
OE
The Output Enable input is active LOW. With chip
enabled, when OE is LOW and WE HIGH, data of
the selected memory location will be available on
the I/O pins. When OE is HIGH, the I/O pins will be
in the high impedance state.
*CE
2
is available on BGA package only.
V62C3184096
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O
1
–I/O
8
Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
GND
Power Supply
Ground
Pin Configurations (Top View)
32-Pin TSOP (Standard)
A11
A9
A8
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
36 BGA
1
A
B
C
D
E
F
G
H
2
3
4
5
6
A
B
C
D
E
F
G
H
1
A0
I/O5
I/O6
VSS
VCC
I/O7
I/O8
A9
2
A1
A2
NB
NB
NB
NB
OE
A10
3
CE2
WE
NC
NB
NB
A18
CE1
A11
4
A3
A4
A5
NB
NB
A17
A16
A12
5
A6
A7
NB
NB
NB
NB
A15
A13
6
A8
I/O1
I/O2
VCC
VSS
I/O3
I/O4
A14
Note:
NC means no connect.
NB means no ball.
TOP VIEW
TOP VIEW
V62C3184096 Rev. 1.1 June 2000
2
MOSEL VITELIC
Part Number Information
V
MOSEL-VITELIC
MANUFACTURED
V62C3184096
62
C
31
8
4096
–
TEMP.
SRAM
FAMILY
OPERATING
VOLTAGE
DENSITY
PWR.
4096K
SPEED
55 ns
70 ns
PKG
BLANK = 0°C to 70°C
I = -40°C to +85°C
62 = STANDARD
C = CMOS PROCESS
31 = 2.7V–3.3V
T = TSOP STANDARD
B = BGA
ORGANIZATION
8 = 8-bit
L = LOW POWER
LL = LOW LOW POWER
Absolute Maximum Ratings
(1)
Symbol
V
CC
V
N
V
DQ
T
BIAS
T
STG
Parameter
Supply Voltage
Input Voltage
Input/Output Voltage Applied
Temperature Under Bias
Storage Temperature
Commercial
-0.5 to + V
CC
+ 0.5
-0.5 to + V
CC
+ 0.5
V
CC
+ 0.3
-10 to +125
-55 to +125
Industrial
-0.5 to + V
CC
+ 0.5
-0.5 to + V
CC
+ 0.5
V
CC
+ 0.3
-65 to +135
-65 to +150
Units
V
V
V
°
C
°
C
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance*
T
A
= 25
°
C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
I/O
= 0V
Max.
6
8
Unit
pF
pF
Truth Table
Mode
Standby
Standby
Output Disable
Read
Write
CE
1
H
X
L
L
L
CE
2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O
Operation
High Z
High Z
High Z
D
OUT
D
IN
NOTE:
1. This parameter is guaranteed and not tested.
NOTE:
X = Don’t Care, L = LOW, H = HIGH
V62C3184096 Rev. 1.1 June 2000
3
MOSEL VITELIC
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 2.7V–3.3V)
Symbol
V
IL
V
IH
I
IL
I
OL
V
OL
V
OH
V62C3184096
Parameter
Input LOW Voltage
(1,2)
Input HIGH Voltage
(1)
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
Test Conditions
Min.
-0.5
2.0
Typ.
—
—
—
—
—
—
Max.
0.4
V
CC
+0.3
1
1
0.4
—
Units
V
V
µ
A
µ
A
V
V
V
CC
= Max, V
IN
= 0V to V
CC
V
CC
= Max, CE
1
= V
IH
, V
OUT
= 0V to V
CC
V
CC
= Min, I
OL
= 2mA
V
CC
= Min, I
OH
= -0.5mA
—
—
—
V
CC
–0.4
Symbol
I
CC1
Parameter
Average Operating Current, CE
1
= V
IL
, CE
2
= V
CC
– 0.2, Output Open,
V
CC
= Max.
TTL Standby Current
CE
1
≥
V
IH
, CE
2
≤
V
IL
, V
CC
= Max., f = 0
CMOS Standby Current, CE
1
≥
V
CC
– 0.2V, CE
2
≤
0.2V,
V
IN
≥
V
CC
– 0.2V or V
IN
≤
0.2V, V
CC
= Max., f = 0
f = fmax
f = 1 MHz
L
LL
L
LL
Comm.
(3)
35
4
0.5
0.3
10
5
Ind.
(3)
40
5
1
1
15
7
Units
mA
I
SB
mA
I
SB1
µA
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. V
IL
(Min.) = -3.0V for pulse width < t
RC
/2.
3. Maximum value.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Timing Reference Levels
Output Load
0 to 2.0V
5 ns
1.1V
see below
AC Test Loads and Waveforms
C
L
*
TTL
C
L
= 30pF + 1TTL Load
* Includes scope and jig capacitance
V62C3184096 Rev. 1.1 June 2000
4
MOSEL VITELIC
Data Retention Characteristics
Symbol
V
DR
V62C3184096
Parameter
V
CC
for Data Retention
CE
1
≥
V
CC
– 0.2V, CE
2
< 0.2V, V
IN
≥
V
CC
– 0.2V,
or V
IN
≤
0.2V
Data Retention Current
CE
1
≥
V
DR
– 0.2V, CE
2
< 0.2V, V
IN
≥
V
CC
– 0.2V,
or V
IN
≤
0.2V, V
DR
= 2.0V
Com’l
Power
Min.
2.0
Typ.
(2)
—
Max.
3.3
Units
V
I
CCDR
L
LL
—
—
—
—
0
t
RC(1)
1
0.5
—
—
—
—
4
3
7
5
—
—
µA
Ind.
L
LL
t
CDR
t
R
Chip Deselect to Data Retention Time
Operation Recovery Time (see Retention Waveform)
ns
ns
NOTES:
1. t
RC
= Read Cycle Time
2. T
A
= +25°C.
Low V
CC
Data Retention Waveform (1) (CE
1
Controlled)
Data Retention Mode
V
CC
2.7V
t
CDR
CE
1
2.2V
CE
1
≥
V
CC
– 0.2V
V
DR
≥
2V
t
R
2.2V
2.7V
Key to Switching Waveforms
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
OUTPUTS
WILL BE
STEADY
WILL BE
CHANGING
FROM H TO L
WILL BE
CHANGING
FROM L TO H
CHANGING:
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
MAY CHANGE
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
V62C3184096 Rev. 1.1 June 2000
5
京公网安备 11010802033920号
EEWORLD
