Integrated
Circuit
Systems, Inc.
ICS93735
DDR Phase Lock Loop Zero Delay Clock Buffer
Recommended Application:
DDR Zero Delay Clock Buffer
Product Description/Features:
• Low skew, low jitter PLL clock driver
• Max frequency supported = 266MHz (DDR 533)
• I
2
C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input
Switching Characteristics:
• CYCLE - CYCLE jitter (66MHz): <120ps
• CYCLE - CYCLE jitter (>100MHz): <65ps
• CYCLE - CYCLE jitter (>200MHz): <75ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 500ps - 700ps
• DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
Functionality
OUTPUTS
AVDD
CLK_INT
CLKT
CLKC
FB_OUTT
2.5V (nom)
L
L
H
L
2.5V (nom)
H
H
L
H
2.5V (nom)
< offset freq* offset freq* offset freq* offset freq*
GND
L
L
H
L
GND
H
H
L
H
* The offset frequency is ~ 20 MHz, varying somewhat from part to part.
INPUTS
PLL State
on
on
off
Bypassed/off
Bypassed/off
48-Pin SSOP
Block Diagram
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
SCLK
SDATA
Control
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
FB_INT
CLK_INT
PLL
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
0579E—08/06/03
ICS93735
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
PWR
OUT
OUT
PWR
IN
IN
-
PWR
PWR
OUT
IN
I/O
Ground
"Complementar y" clocks of differential pair outputs.
"Tr ue" Clock of differential pair outputs.
Power supply 2.5V
Clock input of I
2
C input, 5V tolerant input
"True" reference clock input, 3.3V tolerant input
Not connected
Analog power supply, 2.5V
A n a l o g gr o u n d .
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
Data pin for I
2
C circuitr y 5V tolerant
DESCRIPTION
1, 7, 8, 18, 24, 25,
GND
31, 41, 42, 48
26, 30, 40, 43, 47,
CLKC(9:0)
23, 19, 9, 6, 2
27, 29, 39, 44, 46,
CLKT(9:0)
22, 20, 10, 5, 3
4, 11, 15, 21, 28,
34, 38, 45,
12
13
14, 32, 36
16
17
33
35
37
VDD
SCLK
CLK_INT
N/C
AVDD
AGND
FB_OUTT
FB_INT
SDATA
Byte 0: Output Control
(1= enable, 0 = disable)
Byte 1: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0579E—08/06/03
2
ICS93735
Byte 2: Reserved
(1= enable, 0 = disable)
Byte 3: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT PIN# PWD
Bit 7
-
1
Bit 6
-
1
Bit 5
-
1
Bit 4
-
1
Bit 3
-
1
Bit 2
-
1
Bit 1
-
1
Bit 0
-
1
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 4: Reserved
(1= enable, 0 = disable)
Byte 5: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN# PWD
3,2
1
5,6
1
10, 9
1
20, 19
1
22, 23
1
27, 26
1
-
1
-
1
DESCRIPTION
CLK0 (T&C)
CLK1 (T&C)
CLK2 (T&C)
CLK3 (T&C)
CLK4 (T&C)
CLK9 (T&C)
Reser ved
Reser ved
Byte 6: Reserved
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN# PWD
-
0
-
0
-
0
29, 30
1
39, 40
1
44, 43
1
46, 47
1
-
1
DESCRIPTION
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
CLK8 (T&C)
CLK7 (T&C)
CLK6 (T&C)
CLK5 (T&C)
Reser ved
Note: Don’t write into these registers (7:5), writing into
these registers can cause malfunction.
0579E—08/06/03
3
ICS93735
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will
acknowledge
each byte
one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
Address
D4
(H)
Dummy Command Code
ICS (Slave/Receiver)
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D5
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
Address
D5
(H)
ICS (Slave/Receiver)
ACK
ACK
Dummy Byte Count
ACK
Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK
Byte 6
Byte 6
ACK
ACK
Stop Bit
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop
after any complete byte has been transferred. The Command code and Byte count shown above must be
sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0579E—08/06/03
4
ICS93735
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . .
-0.5V to 3.6V
GND –0.5 V to V
DD
+0.5 V
0°C to +85°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output parameters
T
A
= 0 - 70°C; Supply Voltage AV
DD
, V
DD
= 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
R
T
= 120W, C
L
= 12 pF at 100MHz
I
DD2.5
Operating Supply Current
R
T
= 120W, C
L
= 12 pF at 133MHz
I
DDPD
CL=0 pF
Output High Current
I
OH
V
DD
= 2.5V, V
OUT
= 1V
Output Low Current
I
OL
V
DD
= 2.5V, V
OUT
= 1.2V
High Impedance
I
OZ
V
DD
= 2.7V, V
OUT
= V
DD
or GND
Ouptut Current
V
DD
= min to max, I
OH
= -1mA
V
OH
High-level Output Voltage
V
DD
= 2.3V, I
OH
= -12mA
V
DD
= min to max, I
OH
= 1mA
V
OL
Low-level Output Voltage
V
DD
= 2.3V, I
OH
= 12mA
1
Output Capacitance
V
I
= V
DD
or GND
C
OUT
1. Guaranteed by design, not 100% tested in production.
MIN
TYP
236
263
-33
33
MAX
300
300
100
-29
37
10
2
2.25
1.95
0.05
0.3
3
UNITS
mA
mA
mA
mA
mA
V
0.1
0.4
V
pF
-48
29
0579E—08/06/03
5
DSP and ARM Processors
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