74ALVT162821
Rev. 4 — 24 January 2018
20-bit bus interface D-type flip-flop; positive-edge trigger with
30 Ω termination resistors; 3-state
Product data sheet
1
General description
The 74ALVT162821 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive. It is designed for V
CC
operation
at 2.5 V or 3.3 V with I/O compatibility to 5 V.
The 74ALVT162821 has two 10-bit, edge triggered registers, with each register coupled
to a 3-state output buffer. The two sections of each register are controlled independently
by the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active low output enable (nOE) controls all ten 3-state buffers independent of the
register operation. When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
The 74ALVT162821 is designed with 30 Ω series resistance in both HIGH and LOW
output stages. This design reduces the line noise in applications such as memory
address drivers, clock drivers and bus receivers/transmitters. The series termination
resistors reduce overshoot and undershoot and are ideal for driving memory arrays.
2
Features and benefits
•
Outputs include series resistance of 30 Ω making external termination resistors
unnecessary
•
20-bit positive-edge triggered register
•
5 V I/O compatible
•
Multiple V
CC
and GND pins minimize switching noise
•
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
•
Live insertion and extraction permitted
•
Power-up reset
•
Power-up 3-state
•
Output capability: +12 mA and -12 mA
•
Latch-up protection:
–
JESD17: exceeds 500 mA
•
ESD protection:
–
MIL STD 883, method 3015: exceeds 2000 V
–
MM: exceeds 200 V
Nexperia
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
74ALVT162821
3
Ordering information
Package
Temperature range
Name
SSOP56
TSSOP56
Description
plastic shrink small outline package; 56 leads;
body width 7.5 mm
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
Version
SOT371-1
SOT364-1
-40 °C to +85 °C
Table 1. Ordering information
Type number
74ALVT162821DL
74ALVT162821DGG -40 °C to +85 °C
4
Functional diagram
1OE
1CP
28
2OE
29
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
1
56
EN2
C1
EN4
C3
1D
2
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
55
54
52
51
49
48
47
45
44
43
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
56
1
1CP
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2
42
3
41
5
40
6
38
8
37
9
36
10
34
12
33
13
31
14
30
3D
4
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29
28
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
001aad153
001aad155
Figure 1. Logic symbol
Figure 2. IEC logic symbol
74ALVT162821
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 4 — 24 January 2018
2 / 18
Nexperia
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state
74ALVT162821
5.2 Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4,
1D5, 1D6, 1D7, 1D8, 1D9
1Q0, 1Q1, 1Q2, 1Q3, 1Q4,
1Q5, 1Q6, 1Q7, 1Q8, 1Q9
2D0, 2D1, 2D2, 2D3, 2D4,
2D5, 2D6, 2D7, 2D8, 2D9
2Q0, 2Q1, 2Q2, 2Q3, 2Q4,
2Q5, 2Q6, 2Q7, 2Q8, 2Q9
1OE, 2OE
1CP, 2CP
GND
V
CC
Pin
55, 54, 52, 51, 49,
48, 47, 45, 44, 43
2, 3, 5, 6, 8,
9, 10, 12, 13, 14
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25,
32, 39, 46, 53
7, 22, 35, 50
Description
data inputs
data outputs
data inputs
data outputs
output enable inputs (active LOW)
clock pulse inputs (active rising edge)
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function table
Operating mode
Load and read register
Hold
Disable outputs
Input
nOE
L
L
L
H
H
nCP
↑
↑
NC
NC
↑
nDn
l
h
X
X
nDn
Internal register Output
nQn
L
H
NC
NC
nDn
L
H
NC
Z
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
74ALVT162821
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 4 — 24 January 2018
5 / 18
Microcontroller MCU
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